參數(shù)資料
型號(hào)： AD7851KNZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/36頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 333KSPS 24-DIP
標(biāo)準(zhǔn)包裝： 15
位數(shù)： 14
采樣率（每秒）： 333k
數(shù)據(jù)接口： 8051，QSPI?，串行，SPI? µP
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 89.25mW
電壓電源： 模擬和數(shù)字
工作溫度： 0°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 24-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 24-PDIP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)偽差分，單極；1 個(gè)偽差分，雙極
–5–
REV. B
AD7851
Descriptions that refer to SCLK
↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin
LOW, then the opposite edge of SCLK will apply.
Limit at TMIN, TMAX
Parameter
(A, K Versions)
Unit
Description
fCLKIN
2
500
kHz min
Master Clock Frequency
7
MHz max
fSCLK
3
10
MHz max
Interface Modes 1, 2, 3 (External Serial Clock)
fCLK IN
MHz max
Interface Modes 4, 5 (Internal Serial Clock)
t1
4
100
ns min
CONVST Pulse Width
t2
50
ns max
CONVST
↓ to BUSY↑ Propagation Delay
tCONVERT
3.25
s max
Conversion Time = 20 tCLKIN
t3
–0.4 tSCLK
ns min
SYNC
↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
±0.4 tSCLK
ns min/max
SYNC
↓ to SCLK↓ Setup Time (Continuous SCLK Input)
t4
0.6 tSCLK
ns min
SYNC
↓ to SCLK↓ Setup Time, Interface Mode 4 Only
t5
5
30
ns max
Delay from
SYNC
↓ until DOUT Three-State Disabled
t5A
5
30
ns max
Delay from
SYNC
↓ until DIN Three-State Disabled
t6
5
45
ns max
Data Access Time after SCLK
↓
t7
30
ns min
Data Setup Time prior to SCLK
↑
t8
20
ns min
Data Valid to SCLK Hold Time
t9
6
0.4 tSCLK
ns min
SCLK High Pulse Width (Interface Modes 4 and 5)
t10
6
0.4 tSCLK
ns min
SCLK Low Pulse Width (Interface Modes 4 and 5)
t11
30
ns min
SCLK
↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 tSCLK
ns min/max
(Continuous SCLK) Does Not Apply to Interface Mode 3
t11A
50
ns max
SCLK
↑ to SYNC↑ Hold Time
t12
7
50
ns max
Delay from
SYNC
↑ until DOUT Three-State Enabled
t13
90
ns max
Delay from SCLK
↑ to DIN Being Configured as Output
t14
8
50
ns max
Delay from SCLK
↑ to DIN Being Configured as Input
t15
2.5 tCLKIN
ns max
CAL
↑ to BUSY↑ Delay
t16
2.5 tCLKIN
ns max
CONVST
↓ to BUSY↑ Delay in Calibration Sequence
tCAL
9
41.7
ms typ
Full Self-Calibration Time, Master Clock Dependent
(250026 tCLKIN)
tCAL1
9
37.04
ms typ
Internal DAC Plus System Full-Scale Calibration Time, Master Clock
Dependent (222228 tCLKIN)
tCAL2
9
4.63
ms typ
System Offset Calibration Time, Master Clock Dependent
(27798 tCLKIN)
tDELAY
65
ns max
Delay from CLK to SCLK
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2Mark/space ratio for the master clock input is 40/60 to 60/40.
3For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f
CLKIN.
4The
CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Down section).
5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t
SCLK = 0.5 tCLKIN.
7The time t
12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t 12 as quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
8 The time t
14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true
delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing
that a bus conflict will not occur.
9The typical time specified for the calibration times is for a master clock of 6 MHz.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1 (AV
DD = DVDD = 5.0 V
5%; fCLKIN = 6 MHz, TA = TMIN to TMAX, unless otherwise noted.)
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