參數(shù)資料
型號(hào)： AD7835BS
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： LC2MOS Quad 14-Bit DAC
中文描述： QUAD, SERIAL INPUT LOADING, 14-BIT DAC, PQFP44
封裝： PLASTIC, QFP-44
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 404K
代理商： AD7835BS
AD7834/AD7835
REV. A
–11–
V
OUT
has been disconnected from the DSG pin by the opening
of G
5
but will track the voltage present at DSG via the unity
gain buffer.
Power-On with
LDAC
Low,
CLR
High
In many applications of the AD7834/AD7835
LDAC
will be
kept continuously low, thus updating the DAC after each valid
data transfer. If
LDAC
is low when power is applied, then G
1
is
closed and G
2
is open, thus connecting the output of the DAC
to the input of the output amplifier. G
3
and G
5
will be closed
and G
4
and G
6
open, connecting the amplifier as a unity gain
buffer, as before. V
OUT
is connected to DSG via G
5
and R (a
thin film resistance between DSG and V
OUT
) until V
DD
and V
SS
reach approximately
±
10 V. Then, the internal power-on cir-
cuitry opens G
3
and G
5
and closes G
4
and G
6
. This is the situa-
tion shown in Figure 18. V
OUT
is now at the same voltage as the
DAC output.
DAC
G
1
G
3
V
OUT
R
G
6
G
4
G
5
G
2
DSG
Figure 18. Output Stage with
LDAC
Low
Loading the DAC and Using the
CLR
Input
When
LDAC
goes low, it closes G
1
and opens G
2
as in Fig-
ure 18. The voltage at V
OUT
now follows the voltage present at
the output of the DAC. The output stage remains connected in
this manner until a
CLR
signal is applied. Then the situation
reverts to that shown in Figure 17. Once again V
OUT
remains at
the same voltage as DSG until
LDAC
goes low. This recon-
nects the DAC output to the unity gain buffer.
DSG Voltage Range
During power-on, the V
OUT
pins of the AD7834/AD7835 are
connected to the relevant DSG pins via G
6
and the thin film re-
sistor, R. The DSG potential must obey the max ratings at all
times. Thus, the voltage at DSG must always be within the
range V
SS
– 0.3 V, V
DD
+ 0.3 V. However, in order that the volt-
ages at the V
OUT
pins of the AD7834/AD7835 stay within
±
2 V of the relevant DSG potential during power-on, the
voltage applied to DSG should also be kept within the range
AGND – 2 V, AGND + 2 V.
Once the AD7834/AD7835 has powered on and the on-chip
amplifiers have settled, the situation is as shown as in Figure 17.
Any voltage that is now applied to the DSG pin is buffered by
the same amplifier that buffers the DAC output voltage in nor-
mal operation. Thus, for specified operation, the maximum
voltage that can be applied to the DSG pin increases to the
maximum allowable V
REF
(+) voltage, and the minimum voltage
that can be applied to DSG is the minimum V
REF
(–) voltage. After
the AD7834/AD7835 has fully powered on, the outputs can
track any DSG voltage within this minimum/maximum range.
POWER-ON OF THE AD7834/AD7835
Power should normally be applied to the AD7834/AD7835 in
the following sequence: first V
DD
and V
SS
, then V
CC
, then
V
REF
(+) and V
REF
(–).
CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7834/AD7835 is
shown in Figure 15. It is capable of driving a load of 10 k
in
parallel with 200 pF. G
1
to G
6
are transmission gates that are
used to control the power on voltage present at V
OUT
. G
1
and
G
2
are also used in conjunction with the
CLR
input to set V
OUT
to the user defined voltage present at the DSG pin.
DAC
G
1
G
3
V
OUT
R
G
6
G
4
G
5
G
2
DSG
Figure 15. Block Diagram of AD7834/AD7835 Output Stage
Power-On with
CLR
Low,
LDAC
High
The output stage of the AD7834/AD7835 has been designed to
allow output stability during power-on. If
CLR
is kept low dur-
ing power-on, then just after power is applied to the part, the
situation is as depicted in Figure 16. G
1
, G
4
and G
6
are open
while G
2
, G
3
and G
5
are closed.
DAC
G
1
G
3
V
OUT
R
G
6
G
4
G
5
G
2
DSG
Figure 16. Output Stage with V
DD
< 10 V
V
OUT
is kept within a few hundred millivolts of DSG via G
5
and
R. R is a thin-film resistor between DSG and V
OUT
. The out-
put amplifier is connected as a unity gain buffer via G
3
and the
DSG voltage is applied to the buffer input via G
2
. The amplifi-
ers output is thus at the same voltage as the DSG pin. The out-
put stage remains configured as in Figure 16 until the voltage at
V
DD
and V
SS
reaches approximately
±
10 V. By now the output
amplifier has enough headroom to handle signals at its input
and has also had time to settle. The internal power-on circuitry
opens G
3
and G
5
and closes G
4
and G
6
. This situation is shown
in Figure 17. Now the output amplifier is connected in unity
gain mode via G
4
and G
6
. The DSG voltage is still applied to
the noninverting input via G
2
. This voltage appears at V
OUT
.
DAC
G
1
G
3
V
OUT
R
G
6
G
4
G
5
G
2
DSG
Figure 17. Output Stage with V
DD
> 10 V and
CLR
Low
相關(guān)PDF資料
PDF描述
AD7836AS LC2MOS Quad 14-Bit DAC
AD7836 Quad 14-Bit DAC(14位四通道D/A轉(zhuǎn)換器)
AD7837 Complete, Dual 12-Bit MDACs(完備的雙12位乘法D/A轉(zhuǎn)換器)
AD7838 Octal, 13-Bit Voltage-Output DAC with Parallel Interface(并行接口,8通道13位電壓輸出D/A轉(zhuǎn)換器)
AD7855 3 V to 5 V Single Supply, 600 kSPS 12-Bit Sampling ADCs(單電源,600kSPS12位采樣A/D轉(zhuǎn)換器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7836 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Quad 14-Bit DAC
AD7836AS 制造商:Analog Devices 功能描述:DAC 4-CH R-2R 14-bit 44-Pin MQFP 制造商:Analog Devices 功能描述:IC 14-BIT DAC
AD7836ASZ 功能描述:IC DAC 14BIT QUAD LC2MOS 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
AD7837 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs
AD7837AN 功能描述:IC DAC 12BIT MULT DUAL 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*