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參數(shù)資料
| 型號(hào)： | AD7785BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT SIGMA-DELTA 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 470 |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 3 個(gè)差分，單極；3 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7785EBZ-ND - BOARD EVALUATION FOR AD7785 |
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AD7785
Rev. 0 | Page 17 of 32
FS3
FS2
FS1
FS0
fADC (Hz)
tSETTLE (ms)
Rejection @ 50 Hz/60 Hz (Internal Clock)
1
0
1
16.7
120
80 dB (50 Hz only)
1
0
1
0
16.7
120
65 dB (50 Hz and 60 Hz)
1
0
1
12.5
160
66 dB (50 Hz and 60 Hz)
1
0
10
200
69 dB (50 Hz and 60 Hz)
1
0
1
8.33
240
70 dB (50 Hz and 60 Hz)
1
0
6.25
320
72 dB (50 Hz and 60 Hz)
1
4.17
480
74 dB (50 Hz and 60 Hz)
CONFIGURATION REGISTER
RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710
The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to con-
figure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and
select the analog input channel. Table 15 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit
locations; CON denotes that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in
parentheses indicates the power-on/reset default status of that bit.
CON15
CON14
CON13
CON12
CON11
CON10
CON9
CON8
VBIAS1(0)
VBIAS0(0)
BO(0)
U/B(0)
BOOST(0)
G2(1)
G1(1)
G0(1)
CON7
CON6
CON5
CON4
CON3
CON2
CON1
CON0
REFSEL(0)
0(0)
BUF(1)
0(0)
CH2(0)
CH1(0)
CH0(0)
Table 15. Configuration Register Bit Designations
Bit Location
Bit Name
Description
CON15 to
CON14
VBIAS1 to
VBIAS0
Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AVDD/2. These
bits are used in conjunction with the boost bit.
VBIAS1
VBIAS0
Bias Voltage
0
Bias voltage generator disabled
0
1
Bias voltage connected to AIN1(
)
1
0
Bias voltage connected to AIN2(
)
1
Reserved
CON13
BO
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path
are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only
when the buffer or in-amp is active. The burnout currents are available on Channels AIN1 and AIN2.
CON12
U/B
Unipolar/Bipolar Bit. Set by user to enable unipolar coding. Therefore, a zero differential input results in
0x00000 output, and a full-scale differential input results in 0xFFFFF output. Cleared by the user to enable
bipolar coding. Negative full-scale differential input results in an output code of 0x00000, zero differential
input results in an output code of 0x80000, and a positive full-scale differential input results in an output code
of 0xFFFFF.
CON11
BOOST
This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the bias
voltage generator is increased. This reduces its power-up time.
CON10 to
CON8
G2 to G0
Gain Select Bits.
Written by the user to select the ADC input range as follows:
G2
G1
G0
Gain
ADC Input Range (2.5 V Reference)
0
1 (In-amp not used)
2.5 V
0
1
2 (In-amp not used)
1.25 V
0
1
0
4
625 mV
0
1
8
312.5 mV
1
0
16
156.2 mV
1
0
1
32
78.125 mV
1
0
64
39.06 mV
1
128
19.53 mV
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