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參數(shù)資料
| 型號： | AD774B |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | Complete 12-Bit A/D Converters(完備的12位A/D轉(zhuǎn)換器) |
| 中文描述： | 完整的12位A / D轉(zhuǎn)換器（完備的12位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 335K |
| 代理商： | AD774B |
AD674B/AD774B
REV. B
–8–
CIRCUIT OPERATION
The AD674B and AD774B are complete 12-bit monolithic A/D
converters which require no external components to provide the
complete successive-approximation analog-to-digital conversion
function. A block diagram is shown in Figure 5.
DIGITAL
OUTPUTS
DB11 (MSB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DB0 (LSB)
DB1
DB2
DB3
DB4
DB7
DB6
DB5
DB8
DB9
DB10
STATUS
STS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
AC
CE
REF OUT
REF IN
VEE
BIPOFF
CONTROL
CLOCK
SAR
10V
MSB
LSB
3
S
T
A
T
E
O
U
T
P
U
T
B
U
F
F
E
R
S
N
Y
B
B
L
E
N
Y
B
B
L
E
N
Y
B
B
L
E
A
B
C
DIVIDER
12
12
12
19.95k
N
DAC
COMP
LOGIC
+5V SUPPLY
V
A0
SHORT CYCLE
CHIP ENABLE
+10V REFERENCE
V
+12/+15V SUPPLY
ANALOG COMMON
REFERENCE INPUT
12_
_
BIPOLAR OFFSET
10V SPAN10VIN
20V SPAN20VIN
I
DAC
I
REF
EE
V
12/8
DATA MODE SELECT
CHIP SELECT
CS
READ/ CONVR/C
DIGITAL COMMON DC
AD674B/AD774B
Figure 5. Block Diagram of AD674B and AD774B
When the control section is commanded to initiate a conversion
(as described later), it enables the clock and resets the
successive-approximation register (SAR) to all zeroes. Once a
conversion cycle has begun, it cannot be stopped or restarted
and data is not available from the output buffers. The SAR,
timed by the clock, will sequence through the conversion cycle
and return an end-of-convert flag to the control section. The
control section will then disable the clock, bring the output
status flag low, and enable control functions to allow data read
by external command.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most-significant-bit
(MSB) to least-significant-bit (LSB) to provide an output cur-
rent which accurately balances the input signal current through
the divider network. The comparator determines whether the
addition of each successively-weighted bit current causes the
DAC current sum to be greater or less than the input current; if
the sum is less, the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12-bit binary code
which accurately represents the input signal to within
±
1/2 LSB.
The temperature-compensated reference provides the primary
voltage reference to the DAC and guarantees excellent stability
with both time and temperature. The reference is trimmed to
10.00 volts
±
1%; it can supply up to 2.0 mA to an external load
in addition to the requirements of the reference input resistor
(0.5 mA) and bipolar offset resistor (0.5 mA). Any external load
on the reference must remain constant during conversion. The
thin film application resistors are trimmed to match the fullscale
output current of the DAC. The input divider network provides
a 10 V or 20 V input range. The bipolar offset resistor is
grounded for unipolar operation and connected to the 10 volt
reference for bipolar operation.
DRIVING THE ANALOG INPUT
The AD674B and AD774B are successive-approximation analog-
to-digital converters. During the conversion cycle, the ADC
input current is modulated by the DAC test current at approxi-
mately a 1 MHz rate. Thus it is important to recognize that the
signal source driving the ADC must be capable of holding a
constant output voltage under dynamically-changing load
conditions.
Figure 6. Op Amp—ADC Interface
The closed-loop output impedance of an op amp is equal to the
openloop output impedance (usually a few hundred ohms) di-
vided by the loop gain at the frequency of interest. It is often
assumed that the loop gain of a follower-connected op amp is
sufficiently high to reduce the closed-loop output impedance to
a negligibly small value, particularly if the signal is low fre-
quency. However, the amplifier driving the ADC must either
have sufficient loop gain at 1 MHz to reduce the closed-loop
output impedance to a low value or have low open-loop output
impedance. This can be accomplished by using a wideband op
amp, such as the AD711.
If a sample-hold amplifier is required, the monolithic AD585 or
AD781 is recommended, with the output buffer driving the
AD674B or AD774B input directly. A better alternative is the
AD1674 which is a 10
μ
s
sampling
ADC in the same pinout
as the AD574A, AD674A or AD774B and is functionally
equivalent.
SUPPLY DECOUPLING AND LAYOUT
CONSIDERATION
It is critically important that the power supplies be filtered, well
regulated, and free from high frequency noise. Use of noisy sup-
plies will cause unstable output codes. Switching power supplies
are not recommended for circuits attempting to achieve 12-bit
accuracy unless great care is used in filtering any switching
spikes present in the output. Few millivolts of noise represent
several counts of error in a 12-bit ADC.
Decoupling capacitors should be used on all power supply pins;
the +5 V supply decoupling capacitor should be connected di-
rectly from Pin 1 to Pin 15 (digital common) and the +V
CC
and
–V
EE
pins should be decoupled directly to analog common (Pin
9). A suitable decoupling capacitor is a 4.7
μ
F tantalum type in
parallel with a 0.1
μ
F ceramic disc type.
Circuit layout should attempt to locate the ADC, associated
analog input circuitry, and interconnections as far as possible
from logic circuitry. For this reason, the use of wire-wrap circuit
construction is not recommended. Careful printed-circuit layout
and manufacturing is preferred.
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