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參數(shù)資料
| 型號： | AD774B |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | Complete 12-Bit A/D Converters(完備的12位A/D轉(zhuǎn)換器) |
| 中文描述： | 完整的12位A / D轉(zhuǎn)換器（完備的12位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 335K |
| 代理商： | AD774B |
AD674B/AD774B
REV. B
–10–
TO
OUTPUT
BUFFERS
Q
R
S
Q
S
R
Q
QB
CE
NYBBLE A
ENABLE
NYBBLE B
ENABLE
SAR
RESET
EOC 8
EOC 12
HIGH IF CONVERSION
IN PROGRESS
STATUS
START CONVERT
12/8
R/C
CS
READ
NYBBLE C
ENABLE
NYBBLE B = 0
ENABLE
EN
VALUE OF A0
EN
A0
D
D
CLK EN
Figure 9. Equivalent Internal Logic Circuitry
CONTROL LOGIC
The AD674B and AD774B contain on-chip logic to provide
conversion initiation and data read operations from signals
commonly available in microprocessor systems; this internal
logic circuitry is shown in Figure 9.
The control signals CE,
CS
, and R/
C
control the operation of
the converter. The state of R/
C
when CE and
CS
are both as-
serted determines whether a data read (R/
C
= 1) or a convert
(R/
C
= 0) is in progress. The register control inputs A
0
and
12/
8
control conversion length and data format. If a conversion
is started with A
0
low, a full 12-bit conversion cycle is initiated.
If A
0
is high during a convert start, a shorter 8-bit conversion
cycle results. During data read operations, A
0
determines
whether the three-state buffers containing the 8 MSBs of the
conversion result (A
0
= 0) or the 4 LSBs (A
0
= 1) are enabled.
The 12/
8
pin determines whether the output data is to be orga-
nized as two 8-bit words (12/
8
tied to DIGITAL COMMON)
or a single 12-bit word (12/
8
tied to V
LOGIC
). In the 8-bit mode,
the byte addressed when A
0
is high contains the 4 LSBs from
the conversion followed by four trailing zeroes. This organiza-
tion allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
Table I. Truth Table
CE
CS
R/
C
12/
8
A
0
Operation
0
X
1
1
1
1
1
X
1
0
0
0
0
0
X
X
0
0
1
1
1
X
X
X
X
1
0
0
X
X
0
1
X
0
1
None
None
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
Enable 12-Bit Parallel Output
Enable 8 Most Significant Bits
Enable 4 LSBs +4 Trailing Zeroes
The ADC may be operated in one of two modes, the full-control
mode and the stand-alone mode. The full-control mode utilizes
all the control signals and is useful in systems that address de-
code multiple devices on a single data bus. The stand-alone
mode is useful in systems with dedicated input ports available.
In general, the stand-alone mode is capable of issuing start-con-
vert commands on a more precise basis and, therefore, produces
higher accuracy results. The following sections describe these
two modes in more detail.
FULL-CONTROL MODE
Chip Enable (CE), Chip Select (
CS
) and Read/Convert (R/
C
)
are used to control Convert or Read modes of operation. Either
CE or
CS
may be used to initiate a conversion. The state of R/
C
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