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參數(shù)資料
| 型號(hào)： | AD7747 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | 24-Bit Capacitance-to-Digital Converter with Temperature Sensor |
| 中文描述： | 24位的電容數(shù)字轉(zhuǎn)換器的溫度傳感器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 200K |
| 代理商： | AD7747 |
AD7747
Preliminary Technical Data
REGISTER DESCRIPTIONS
The master can write to or read from all of the AD7747 registers
except the address pointer register, which is a write-only
register. The address pointer register determines which register
the next read or write operation accesses. All communications
with the part through the bus start with an access to the address
pointer register. After the part has been accessed over the bus
Rev. PrC | Page 12 of 20
and a read/write operation is selected, the address pointer
register is set up. The address pointer register determines from
or to which register the operation takes place. A read/write
operation is performed from/to the target address, which then
increments to the next address until a stop command on the bus
is performed.
Table 8. Register Summary
Address
Pointer
(Dec) (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Dir
Default Value
-
0
-
0
-
0
-
0
-
0
RDY
1
RDYVT
1
RDYCAP
1
Status
0
0x00
R
Cap Data H
1
0x01
R
Capacitive channel data—high byte, 0x00
Cap Data M
2
0x02
R
Capacitive channel data—middle byte, 0x00
Cap Data L
3
0x03
R
Capacitive channel data—low byte, 0x00
VT Data H
4
0x04
R
Voltage/temperature channel data—high byte, 0x00
VT Data M
5
0x05
R
Voltage/temperature channel data—middle byte, 0x00
VT Data L
6
0x06
R
Voltage/temperature channel data—low byte, 0x00
CAPEN
0
VTEN
0
-
0
VTFS1
1
DACAENA
0
DACBENB
0
-
0
CAPDIFF
0
VTMD0
0
-
0
CAPFS2
1
-
0
-
0
-
0
-
0
-
0
-
0
-
0
Cap Setup
7
0x07
R/W
VTMD1
0
-
0
VTFS0
0
-
0
-
0
EXTREF
0
-
0
CAPFS1
0
VTSHORT
0
EXCLVL1
1
MD1
0
VTCHOP
0
EXCLVL0
1
MD0
0
VT Setup
8
0x08
R/W
EXCDAC
0
CAPFS0
0
DACA—6-Bit Value
0x00
DACB—6-Bit Value
0x00
EXCEN
0
MD2
0
EXC Setup
9
0x09
R/W
Configuration
10
0x0A R/W
Cap DAC A
11
0x0B
R/W
Cap DAC B
12
0x0C R/W
Cap Offset H
13
0x0D R/W
Capacitive offset calibration—high byte, 0x80
Cap Offset L
14
0x0E
R/W
Capacitive offset calibration—low byte, 0x00
Cap Gain H
15
0x0F
R/W
Capacitive gain calibration—high byte, factory calibrated
Cap Gain L
16
0x10
R/W
Capacitive gain calibration—low byte, factory calibrated
Volt Gain H
17
0x11
R/W
Voltage gain calibration—high byte, factory calibrated
Volt Gain L
18
0x12
R/W
Voltage gain calibration—low byte, factory calibrated
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