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參數(shù)資料
| 型號： | AD7747 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | 24-Bit Capacitance-to-Digital Converter with Temperature Sensor |
| 中文描述： | 24位的電容數(shù)字轉(zhuǎn)換器的溫度傳感器 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | AD7747 |
Preliminary Technical Data
AD7747
internal register address. Thus, subsequent transmitted data
bytes are loaded into sequentially incremented addresses.
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond
exactly as outlined above for a start condition, that is, a repeated
start condition is treated the same as a start condition. When a
master device issues a stop condition, it relinquishes control of
the bus, allowing another master device to take control of the
bus. Hence, a master wanting to retain control of the bus issues
successive start conditions known as repeated start conditions.
AD7747 RESET
To reset the AD7747 without having to reset the entire I
2
C bus,
an explicit reset command is provided. This uses a particular
address pointer word as a command word to reset the part and
upload all default settings. The AD7747 does not respond to the
I
2
C bus commands (do not acknowledge) during the default
values upload for approximately 150 μs (max 200 μs).
The reset command address word is 0xBF.
Rev. PrC| Page 11 of 20
GENERAL CALL
When a master issues a slave address consisting of seven 0s with
the eighth bit (R/W bit) set to 0, this is known as the general call
address. The general call address is for addressing every device
connected to the I
2
C bus. The AD7747 acknowledges this
address and read in the following data byte.
If the second byte is 0x06, the AD7747 is reset, completely
uploading all default values. The AD7747 does not respond to
the I
2
C bus commands (do not acknowledge) during the default
values upload for approximately 150 μs (max 200 μs).
The AD7747 does not acknowledge any other general call
commands.
1–7
8
9
1
–7
8
9
1–7
8
9
P
S
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
0
Figure 10. Bus Data Transfer
DATA
A(S)
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
P
S
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S)
A(M)
0
Figure 11. Write and Read Sequences
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