參數(shù)資料
型號(hào)： AD7715
廠商： Analog Devices, Inc.
英文描述： 3 V/5 V, 450 mA 16-Bit, Sigma-Delta ADC(16位∑△A/D轉(zhuǎn)換器)
中文描述： 3伏/ 5伏，450毫安16位Σ-Δ模數(shù)轉(zhuǎn)換器（16位Σ△的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 11/31頁(yè)
文件大?。?/td> 254K
代理商： AD7715
AD7715
–11–
REV. B
Table IV. Output Update Rates
CLK*
FS1
FS0
Output Update Rate
–3dB Filter Cutoff
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20Hz
25Hz
100Hz
200Hz
50Hz
60Hz
250Hz
500Hz
5.24Hz
6.55Hz
26.2Hz
52.4Hz
13.1Hz
15.7Hz
65.5Hz
131Hz
Default Status
*Assumes correct clock frequency at MCLK IN pin
B
/U
Bipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On or
RESET
) status of this bit. A 1 in this bit selects unipolar operation.
Buffer Control. With this bit low, the on-chip buffer on the analog input is shorted out. With the buffer
shorted out, the current flowing in the AV
DD
line is reduced to 250
μ
A (all gains at f
CLK IN
= 1 MHz and gain
of 1 or 2 at f
CLK IN
= 2.4576 MHz) or 500
μ
A (gains of 32 and 128 @ f
CLK IN
= 2.4576 MHz) and the output
noise from the part is at its lowest. When this bit is high, the on-chip buffer is in series with the analog input
allowing the input to handle higher source impedances.
Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the
calibration control logic are held in a reset state and the analog modulator is also held in its reset state. When
this bit goes low, the modulator and filter start to process data and a valid word is available in 3
×
1/(output
update rate), i.e., the settling-time of the filter. This FSYNC bit does not affect the digital interface and does
not reset the
DRDY
output if it is low.
BUF
FSYNC
Test Register (RS1, RS0 = 1, 0)
The part contains a Test Register which is used in testing the device. The user is advised not to change the status of any of the
bits in this register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and
will not operate correctly. If the part enters one of its test modes, exercising
RESET
will exit the part from the mode. An alterna-
tive scheme for getting the part out of one of its test modes, is to reset the interface by writing 32 successive 1s to the part and
then load all 0s to the Test Register.
Data Register (RS1, RS0 = 1, 1)
The Data Register on the part is a read-only 16-bit register which contains the most up-to-date conversion result from the
AD7715. If the Communications Register data sets up the part for a write operation to this register, a write operation must actu-
ally take place to return the part to where it is expecting a write operation to the Communications Register (the default state of
the interface). However, the 16 bits of data written to the part will be ignored by the AD7715.
OUTPUT NOISE
AD7715-5
Table V shows the AD7715-5 output rms noise for the selectable notch and –3dB frequencies for the part, as selected by FS1
and FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a V
REF
of +2.5V. These numbers are
typical and are generated at a differential analog input voltage of 0V with the part used in unbuffered mode (BUF bit of the
Setup Register = 0). Table VI meanwhile shows the output
peak-to-peak
noise for the selectable notch and –3dB frequencies for
the part.
It is important to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated
based on rms noise but on peak-to-peak noise
. The numbers given are for the bipolar input ranges with a V
REF
of +2.5V and for the
BUF bit of the Setup Register = 0. These numbers are typical, are generated at an analog input voltage of 0V and are rounded
to the nearest LSB.
Meanwhile, Table VII and Table VIII show rms noise and peak-to-peak resolution respectively with the AD7715-5 operating
under the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1).
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