參數(shù)資料
型號(hào): AD7711AAR
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: LC2MOS Signal Conditioning ADC with RTD Current Source
中文描述: 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝: SOIC-24
文件頁(yè)數(shù): 24/27頁(yè)
文件大?。?/td> 222K
代理商: AD7711AAR
REV. C
AD7711A
–24–
SIMPLIFYING THE EXTERNAL CLOCKING MODE
INTERFACE
In many applications, the user may not require the facility of
writing to the on-chip calibration registers. In this case, the
serial interface to the AD7711A in external clocking mode can
be simplified by connecting the
TFS
line to the A0 input of the
AD7711A (see Figure 14). This means that any write to the
device will load data to the control register (since A0 is low
while
TFS
is low) and any read to the device will access data
from the output data register or from the calibration registers
(since A0 is high while
RFS
is low). It should be noted that in
this arrangement the user does not have the capability of reading
from the control register.
AD7711A
RFS
SDATA
SCLK
TFS
A0
FOUR
INTERFACE
LINES
Figure 14. Simplified Interface with
TFS
Connected to A0
Another method of simplifying the interface is to generate the
TFS
signal from an inverted
RFS
signal. However, generating
the signals the opposite way around (
RFS
from an inverted
TFS
) will cause writing errors.
MICROCOMPUTER/MICROPROCESSOR INTERFACING
The AD7711A’s flexible serial interface allows for easy interface
to most microcomputers and microprocessors. Figure 15 shows
a flowchart diagram for a typical programming sequence for
reading data from the AD7711A to a microcomputer while
Figure 16 shows a flowchart diagram for writing data to the
AD7711A. Figures 17, 18 and 19 show some typical interface
circuits.
The flowchart of Figure 15 is for continuous read operations
from the AD7711A output register. In the example shown, the
DRDY
line is continuously polled. Depending on the micropro-
cessor configuration, the
DRDY
line may come to an interrupt
input in which case the
DRDY
will automatically generate an
interrupt without being polled. The reading of the serial buffer
could be anything from one read operation up to three read
operations (where 24 bits of data are read into an 8-bit serial
register). A read operation to the control/calibration registers is
similar but in this case the status of
DRDY
can be ignored. The
A0 line is brought low when the
RFS
line is brought low when
reading from the control register.
The flowchart also shows the bits being reversed after they have
been read in from the serial port. This depends on whether the
microprocessor expects the MSB of the word first or the LSB of
the word first. The AD7711A outputs the MSB first.
The flowchart in Figure 16 is for a single 24-bit write operation
to the AD7711A control or calibration registers. This shows
data being transferred from data memory to the accumulator
before being written to the serial buffer. Some microprocessor
systems will allow data to be written directly to the serial buffer
from data memory. The writing of data to the serial buffer from
the accumulator will generally consist of either two or three
write operations, depending on the size of the serial buffer.
NO
YES
BRING
RFS
LOW
3
3
REVERSE
ORDER OF BITS
BRING
RFS
HIGH
POLL
DRDY
CONFIGURE &
INITIALIZE
m
C/
m
P
SERIAL PORT
DRDY
LOW
BRING
RFS
,
TFS
HIGH
START
READ
SERIAL BUFFER
Figure 15. Flowchart for Continuous Read Operations to
the AD7711A
The flowchart also shows the option of the bits being reversed
before being written to the serial buffer. This depends on
whether the first bit transmitted by the microprocessor is the
MSB or the LSB. The AD7711A expects the MSB as the first
bit in the data stream. In cases where the data is being read or
being written in bytes and the data has to be reversed, the bits
will have to be reversed for every byte.
相關(guān)PDF資料
PDF描述
AD7711ASQ LC2MOS Signal Conditioning ADC with RTD Current Source
AD7711A* LC2MOS Signal Conditioning ADC with RTD Current Source
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