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參數(shù)資料
| 型號： | AD7711AAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Signal Conditioning ADC with RTD Current Source |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 222K |
| 代理商： | AD7711AAR |
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REV. C
AD7711A
–14–
Input Sample Rate
The modulator sample frequency for the device remains at
f
CLK IN
/512 (19.5 kHz @ f
CLK IN
= 10 MHz) regardless of the
selected gain. However, gains greater than
×
1 are achieved by a
combination of multiple input samples per modulator cycle and
a scaling of the ratio of reference capacitor to input capacitor.
As a result of the multiple sampling, the input sample rate of
the device varies with the selected gain (see Table III). The
effective input impedance is 1/C
×
f
S
where C is the input sam-
pling capacitance and f
S
is the input sample rate.
Table III. Input Sampling Frequency vs. Gain
Gain
Input Sampling Frequency (f
S
)
f
CLK IN
/256 (39 kHz @ f
CLK IN
= 10 MHz)
2
×
f
CLK IN
/256 (78 kHz @ f
CLK IN
= 10 MHz)
4
×
f
CLK IN
/256 (156 kHz @ f
CLK IN
= 10 MHz)
8
×
f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
8
×
f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
8
×
f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
8
×
f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
8
×
f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
1
2
4
8
16
32
64
128
DIGITAL FILTERING
The AD7711A’s digital filter behaves like a similar analog filter,
with a few minor differences.
First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7711A has
overrange headroom built into the sigma-delta modulator and
digital filter which allows overrange excursions of 5% above the
analog input range. If noise signals are larger than this, consid-
eration should be given to analog input filtering, or to reducing
the input channel voltage so that its full scale is half that of the
analog input channel full scale. This will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).
Filter Characteristics
The cutoff frequency of the digital filter is determined by the
value loaded to bits FS0 to FS11 in the control register. At the
maximum clock frequency of 10 MHz, the minimum cutoff
frequency of the filter is 2.58 Hz while the maximum program-
mable cutoff frequency is 269 Hz.
Figure 6 shows the filter frequency response for a cutoff fre-
quency of 2.62 Hz, which corresponds to a first filter notch fre-
quency of 10 Hz. This is a (sinx/x)
3
response (also called sinc
3
)
that provides >100 dB of 50 Hz and 60 Hz rejection. Program-
ming a different cutoff frequency via FS0–FS11 does not alter
the profile of the filter response, it changes the frequency of the
notches as outlined in the Control Register section.
FREQUENCY – Hz
0
–2400
70
10
G
20
30
40
50
60
–20
–120
–180
–200
–220
–60
–100
–40
–80
–140
–160
Figure 6. Frequency Response of AD7711A Filter
Since the AD7711A contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data on the output will be invalid after a step change until the
settling time has elapsed. The settling time depends upon the
notch frequency chosen for the filter. The output data rate
equates to this filter notch frequency, and the settling time of
the filter to a full-scale step input is four times the output data
period. In applications using both input channels, the settling
time of the filter must be allowed to elapse before data from the
second channel is accessed.
Post Filtering
The on-chip modulator provides samples at a 19.5 kHz output
rate. The on-chip digital filter decimates these samples to
provide data at an output rate that corresponds to the pro-
grammed first notch frequency of the filter. Since the output
data rate exceeds the Nyquist criterion, the output rate for a
given bandwidth will satisfy most application requirements.
However, there may be some applications which require a
higher data rate for a given bandwidth and noise performance.
Applications that need this higher data rate will require some
post filtering following the digital filter of the AD7711A.
For example, if the required bandwidth is 7.86 Hz but the re-
quired update rate is 100 Hz, the data can be taken from the
AD7711A at the 100 Hz rate giving a –3 dB bandwidth of
26.2 Hz. Post filtering can be applied to this to reduce the band-
width and output noise, to the 7.86 Hz bandwidth level, while
maintaining an output rate of 100 Hz.
Post filtering can also be used to reduce the output noise from
the device for bandwidths below 2.62 Hz. At a gain of 128, the
output rms noise is 250 nV. This is essentially device noise or
white noise, and since the input is chopped, the noise has a flat
frequency response. By reducing the bandwidth below 2.62 Hz,
the noise in the resultant passband can be reduced. A reduction
in bandwidth by a factor of two results in a
√
2
reduction in the
output rms noise. This additional filtering will result in a longer
settling time.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD7711AARZ | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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| AD7711ANZ | 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA |
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