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參數(shù)資料
| 型號： | AD7011 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS, ADC p/4 DQPSK Baseband Transmit Port |
| 中文描述： | 的CMOS ADC的p / 4 DQPSK基帶傳輸端口 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 389K |
| 代理商： | AD7011 |
AD7011
REV. B
–7–
PIN FUNCT ION DE SCRIPT ION
SSOP Pin
Number
Mnemonic
Function
POWE R SUPPLY
19
5
14, 18, 23
6
V
AA
V
DD
AGND
DGND
Positive power supply for analog section.
Positive power supply for digital section.
Analog ground for transmit section.
Digital ground for transmit section.
ANALOG SIGNAL AND RE FE RE NCE
13
BYPASS
16, 17
IT x,
ITx
Reference decoupling output. A decoupling capacitor should be connected between this pin and AGND.
Differential analog outputs for the I channel, representing true and complementary outputs of the I
waveform.
Differential analog outputs for the Q channel, representing true and complementary outputs of the Q
waveform.
21, 20
QT x,
QTx
T RANSMIT INT E RFACE AND CONT ROL
7
MCLK
Master clock, digital input. When operating in Mode 0 (T IA Digital mode), this pin should be driven by a
3.1104 MHz CMOS compatible clock source in digital mode and by 2.56 MHz CMOS compatible clock
source for analog mode.
T his is a dual function digital input/output. When operating in Mode 0 (T IA Digital mode), this pin is
configured as a digital output, transmit clock. T his may be used to clock in transmit data at 48.6 kHz. When
operating in Mode 1 (analog mode), this pin is configured as a digital input, FRAME. T his is used to frame
the clocking in of 16-bit words when bypassing the
π
/4 DQPSK modulator and directly loading the I and Q
10-bit DACs.
T his is a dual function digital input. When operating in Mode 0 (T IA Digital mode), this pin is used to
clock in transmit data on the falling edge of T xCLK at a rate of 48.6 kHz. When operating in Mode 1
(Analog mode), I data is clocked in on the rising edge of MCLK . T his data bypasses the
π
/4 DQPSK modu-
lator and is loaded into the 10-bit I DAC.
BIN (QDAT A) T his is a dual function digital input. When operating in Mode 0 (T IA Digital mode), this input is used to ini-
tiate the ramping up (BIN high) or down (BIN low) of the I and Q waveforms. When operating in Mode 1
(Analog mode), Q data is clocked in on the rising edge of MCLK . T his data bypasses the
π
/4 DQPSK modu-
lator and is loaded into the 10-bit Q DAC.
BOUT
Burst Out, digital output. T his is the BIN input delayed by the pipeline delay, both digital and analog, of the
AD7011. T his can be used to turn on and off the RF amplifiers in synchronization with the I and Q waveforms.
POWER
T ransmit sleep mode, digital input. When this goes low, the AD7011 goes into sleep mode, drawing minimal
current. When this pin goes high, the AD7011 is brought out of sleep mode and initiates a self-calibration
routine to eliminate the offset between IT x &
ITx
and the offset between QT x &
QTx
.
READY
T ransmit ready, digital output. T his output goes high once the self-calibration routine is complete.
MODE1,
Mode control, digital inputs. T hese are used to enter the AD7011 into three different operating modes,
MODE2
see T able I.
NC
No Connects. T hese pins are no connects and should not be used as routes for other circuit signals.
3
T xCLK
(FRAME)
4
T xDAT A
(IDAT A)
2
24
1
12
9, 11
8, 10, 15, 22
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