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參數(shù)資料
| 型號(hào)： | AD7011 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS, ADC p/4 DQPSK Baseband Transmit Port |
| 中文描述： | 的CMOS ADC的p / 4 DQPSK基帶傳輸端口 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 389K |
| 代理商： | AD7011 |
AD7011
REV. B
–5–
ANALOGMODE TIMNG
Parameter
Limit at T
A
= –40
°
C to +85
°
C
Units
Description
t
20
t
21
15
15
15t
1
16t
1
15
15
ns min
ns min
ns max
ns
ns min
ns min
MCLK Rising Edge to FRAME Setup T ime.
MCLK Rising Edge to FRAME Hold T ime.
t
22
t
23
t
24
FRAME Cycle T ime.
MCLK Rising Edge to Data Setup T ime.
MCLK Rising Edge to Data Hold T ime.
(V
AA
= V
DD
= +5 V
6
10%. AGND = DGND = 0 V. All specifications are T
MN
to T
MAX
unless
otherwse noted.)
MCLK
t
20
FRAME
I DATA
DB9
DB8
DB1
DB0
DB9
DB8
DB7
Q DATA
DB9
DB8
DB1
DB0
DB9
DB8
DB7
t
23
t
24
AAAAAA
AAAAAA
AAAAAAA
t
21
t
22
Figure 6. Analog Mode Serial Interface Timing
Q
I
MODULAR OUTPUT
DURING FTEST
Figure 7. Modulator State During FTEST
T able I.
MODE 1
MODE 2
Operation
0
1
0
1
0
0
1
1
Digital T IA Mode
Analog Mode
FT EST
Factory T est, Reserved
T able II.
Mode of Operation
MODE 1
MODE 2
MCLK
Digital Bit Rate
DAC Update Rate
Digital Mode
Analog Mode
0
1
0
0
3.1104 MHz
2.56 MHz
48.6 kHz
N/A
N/A
160 kHz
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