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參數(shù)資料
| 型號(hào)： | AD6435 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ADSL（Asymmetric digital Subscriber Line）Chipset(非對(duì)稱數(shù)字用戶鏈路芯片組) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 89K |
| 代理商： | AD6435 |
AD6435
–8–
REV. 0
CO/RT INT E RFACE T IMING
Simplex Serial Port
T he simplex serial port consists of four pins, two outputs,
SIMPLX _RX and SIMPLX _CLK O, and two inputs, SIMPLX _
T X and SIMPL X _CL K I. T he serial clock rate is completely
variable between 8 kbps and 12.288 Mbps. T he interface
operates differently at the CO and RT locations.
SIMPLX_CLKO
SIMPLX_RX
DTIR XMT
RT RECEIVE
VALID DATA
t
SRX-S
t
SRX-H
CO XMT
DTIR RECEIVE
SIMPLX_CLKI
SIMPLX_TX
VALID DATA
t
STX-S
t
STX-H
Figure 3. Simplex Serial Port
T able II. T X Serial I/F T iming
Parameter
Description
T yp
t
SRX -S
Setup T ime of SIMPLX _RX from
Falling Edge of SIMPLX _CLK O
Hold T ime of SIMPLX _RX from
Falling Edge of SIMPLX _CLK O
Setup T ime of SIMPLX _T X from
Rising Edge of SIMPLX _CLK I
Hold T ime of SIMPLX _T X from
Rising Edge of SIMPLX _CLK I
5 ns
t
SRX -H
5 ns
t
ST X -S
5 ns
t
ST X -H
5 ns
At the CO, the two input pins SIMPLX _T X and SIMPLX _CLK I
are used while the two output pins SIMPLX _RX and SIMPL X _
CLK O are not functionally connected. T he interface can oper-
ate at a continuous data stream into SIMPLX _RX at a fixed
frequency between 8 kbps and 12.288 Mbps. T he data rate is
set while the DT IR is in reset and does not change without
going into the reset state again.
At the RT , the two output pins SIMPLX _RX and SIMPLX _
CL K O are used while the two input pins SIMPL X _T X and
SIMPLX _CLK I are not functionally connected. T he interface can
operate at a continuous data stream out of SIMPLX _RX at a
fixed frequency between 8 kbps and 12.288 Mbps. T he data
rate is set while the DT IR is in reset and does not change with-
out going into the reset state again.
For the Simplex Rx channel, data is driven out of the AD6435
on the positive edge of the respective CLK O signal and should
be sampled by the external circuit on the negative edge.
For the Simplex T x channel, the data is sampled by the AD6435
on the positive edge of the respective CLK O signal and should
be driven by the external circuit on the negative edge.
Duplex Serial Port
T he duplex serial port consists of four pins, two outputs,
DUPLX _RX and DUPLX _CLK O, and two inputs, DUPLX _T X
and DUPLX _CLK I. T he serial clock rate is completely variable
between 8 kbps and 4.096 Mbps. T he interface operates identi-
cally at the CO and RT locations. T he input interface can ac-
cept a continuous stream of data at a fixed frequency within the
duplex rate. T he output interface on the other end transmits the
same continuous stream of data at the same fixed frequency.
T his frequency is established and programmed into the registers
by the DSP during reset.
For the Duplex Rx channel, data is driven out of the AD6435
on the positive edge of the respective CLK O signal and should
be sampled by the external circuit on the negative edge.
For the Duplex T x channel, the data is sampled by the AD6435
on the positive edge of the respective CLK O signal and should
be driven by the external circuit on the negative edge.
DUPLX_CLKO
DUPLX_RX
DTIR XMT
CO/RT RECEIVE
VALID DATA
t
DRX-S
t
DRX-H
CO/RT XMT
DTIR RECEIVE
DUPLX_CLKI
DUPLX_TX
VALID DATA
t
DTX-S
t
DTX-H
Figure 4. Duplex Serial Port
T able III. T X Serial I/F T iming
Parameter
Description
T yp
t
DRX -S
Setup T ime of DUPLX _RX from
Falling Edge of DUPLX _CLK O
Hold T ime of DUPLX _RX from
Falling Edge of DUPLX _CLK O
Setup T ime of DUPLX _T X from
Rising Edge of DUPLX _CLK I
Hold T ime of DUPLX _T X from
Rising Edge of DUPLX _CLK I
5 ns
t
DRX -H
5 ns
t
DT X -S
5 ns
t
DT X -H
5 ns
INT E RLE AVE RAM INT E RFACE
T he DT IR (DIA) Interfaces an external 32k
×
8 Interleave
RAM. T he interleave RAM interface consists of M_A(14:0),
M_D(7:0), NM_WE, and NM_OE. When operating at 3.3 V
RAM must have access time less than 50 ns. For further infor-
mation concerning the operation of the RAM access, consult the
DIA specification.
DME INT E RFACE T IMING
All signals transmitted by the DME to the DT IR are transmit-
ted on the rising edge and sampled on the falling edge except for
the T X _DREQ signal that is transmitted by the DME on the
falling edge and sampled by the DT IR on the rising edge. All
output signals from the DT IR to the DME are transmitted by
the DT IR on the rising edge and received by the DME on the
rising edge.
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