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參數(shù)資料
| 型號(hào)： | AD6435 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ADSL（Asymmetric digital Subscriber Line）Chipset(非對(duì)稱數(shù)字用戶鏈路芯片組) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 89K |
| 代理商： | AD6435 |
AD6435
–10–
REV. 0
T X Serial Port
T he T X serial interface between the DME and DT IR uses five
(5) signals:
T X _RX _SCLK :
Serial clock provided by DME.
T X _DREQ:
Data request provided by DME.
T X _FRM:
Frame strobe provided by DME.
T X _BS:
Byte strobe provided by DT IR.
T X _SDAT A:
Serial data provided by DT IR.
RX Serial Interface
T he RX serial interface between the DME and DT IR uses five
(5) signals:
T X _RX _SCLK :
RX _FRMRX _FRM:
RX _BS:
RX _SDAT A:
RX _DREQ:
Serial clock provided by DME.
Frame strobe provided by DME.
Byte strobe provided by DME.
Serial data provided by DME.
Data request provided by DT IR.
DSP PORT
T he DSP port consists of a 14-bit address bus, A[13:0], a 16-bit
data bus, D[15:0], DSP_CL K and three bus control pins,
NRD, NWR, NCS.
Parameter
Min
Max
Unit
Read Operation
Timing Requirements
:
t
RDD
t
AA
t
RDH
NRD Low to Data Valid
A0–A13, NCS to Data Valid
Data Hold from NRD High
8
14
ns
ns
ns
0
Switching Characteristics:
t
RP
t
CRD
t
ASR
t
RDA
t
RWR
NRD Pulsewidth
DSP_CLK High to NRD Low
A0–A13, NCS Setup before NRD Low
A0–A13, NCS Hold after NRD Deasserted
NRD High to NRD or NWR Low
12
3
2
5
12
ns
ns
ns
ns
ns
16
NOT E:
DSP clock 28 MHz (35.7 ns)
t
RDD
t
RDH
DSP_CLK
A0–A13
D
t
RDA
t
RWR
t
RP
t
ASR
t
CRD
t
AA
NRD
NWR
NCS
Figure 7. Read Operation
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