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參數(shù)資料
| 型號(hào)： | AD6435 |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ADSL（Asymmetric digital Subscriber Line）Chipset(非對(duì)稱(chēng)數(shù)字用戶(hù)鏈路芯片組) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | AD6435 |
AD6435
–7–
REV. 0
T able I. Interface Descriptions
Name
Description
duplex_rx
Duplex data output from the AD6435 (i.e.,
data received).
Clock associated with duplex_rx (output).
Duplex data input to the AD6435 (i.e.,
data to be transmitted).
Clock associated with duplex_tx input.
Simplex data output from the AD6435.
AT U-R: downstream data received.
AT U-C: not used.
Clock associated with simplex_rx (output).
Simplex data input to the AD6435.
AT U-R: not used.
AT U-C: downstream data to be sent.
Clock associated with simplex_tx (input).
duplex_clko
duplex_tx
duplex_clki
simplex_rx
simplex_clko
simplex_tx
simplex_clki
ELASTIC STORE
AD6435
PAYLOAD DATA OUT
PAYLOAD DATA IN
DRIVER
AD816
DRIVER/RECEIVER
AD6436
AD6437
RECEIVER
FRAMER
EOC
REMOVE
FRAMER
CRC
CRC
DETECT
UNSCRAMBLE
SCRAMBLER
FEC
ENCODE
FEC
DECODE
DE-INTERLEAVER
INTERLEAVER
RAM
ARBITRATION
RAM
EOC INSERT
SYNC
TONE
SHUFFLE
CONSTELLATION
ENCODE
INVERSE
FFT
INTERPOLATE
TONE
REORDER
CONSTELLATION
DECODE
FFT
DECIMATE
& TDQ
DAC
ADC
SERIAL DAC
(TO VCXO)
CONTROL
FILTER
FILTER
PGA
HYBRID
POTS
SPLITTER
Figure 2. AD20msp910 System Block Diagram
In general tx clock signals (i.e., duplex_clcki, simplex_clki)
are input to the AD6435, while the received data clock sig-
nals (duplex_clko, simplex_clko) are outputs. In other words,
the sending modem (at AT U-C or AT U-R) supplies the clock
to the AD6435, and the receiving modem’s AD6435 recovers it
(using a digital phase locked loop) and supplies it to the external
system. T he channels all have separate—independent—clocks.
T here are two exceptions; the duplex streams can be “l(fā)ocked” with
a single clock or, in a “one down/one up” system typical for data
applications, the unused DPLL can be programmed to be a clock
source at the desired data rate for the tx channel.
T o avoid overflow/underflow of internal buffers, the clock rate
of the streams should be held roughly constant. As such, al-
though a degree of jitter or rate variation is supported, pure
burst-mode is not, and idle cell insertion (deletion) is necessary
and must be implemented by an external device.
Alternatively, the buffering multiplex/demultiplex and bit-stuff/
rob operations may be bypassed (T ICL bypass operation).
T hese blocks are then powered down, reducing the AD6435’s
power consumption. T he interface presented is then a “raw”
stream of upstream and downstream data. As the elastic store
has been disabled, these have the relic of the ADSL line super-
frame structure, and will show an irregular clock (with a pause
for every 69th frame). T his mode is compatible with the AD6442
DIA interface and is suited to packet (e.g., AT M) operation. It
results in a slight power saving.
NB: Although the AD6435 can implement the T 1.413 stan-
dard, and includes the required framing/interfacing (e.g.,
elastic store, bit-stuffing/robbing), it does not support the full
optional suite of seven bearer streams (ASx and L Sx) and
associated multiplexing/demultiplexing as defined in T 1.413.
Instead, simple synchronous data streams are provided. T hese
are essentially AS0 (simplex) and LS0 (duplex) but with vari-
able rate or rate adaptive (not merely fixed multiples of standard
PDH rates, as per Chapter 5 of T 1.413). Additionally, the “du-
plex” stream can be treated as two independent streams, one up
and one down. Indeed, in many applications, only one stream in
each direction is required; in this case, the downstream duplex
path is not used.
Further T C-layer operations can be defined by the system for
their requirements (e.g., for V.35, AT M or 10BaseT ), and sim-
ply interfaced to the AD6435 serial ports.
INT E RFACE T IMING
T he DT IR contains simplex (AS) and duplex (LS) channels
that interface with the Central Office (CO) and Remote T ermi-
nal (RT ). T he DT IR contains a transmit serial port in which the
DT IR transmits a bit stream to the DME and a receive serial
port in which DT IR receives a serial bit stream from the DME.
Since the DIA is being treated as a black box, the T ICL-DIA
interface will be defined here. T his interface is similar to the
DIA-DME transmit and receive interfaces. T he DT IR also
interfaces with a 32k
×
8 Interleave RAM. T he DT IR also has a
DSP host port that allows a DSP to monitor the DT IR and
control the data through the device.
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