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| 型號： | AD5735ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC QUAD VOLT CUR 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 設(shè)置時間： | 18µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，4 電壓 |
| 采樣率（每秒）： | * |
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Data Sheet
AD5735
Rev. C | Page 13 of 48
Pin No.
Mnemonic
Description
14
CLEAR
Active High, Edge Sensitive Input. When this pin is asserted, the output current and voltage are set to the
programmed clear code bit setting. Only channels enabled to be cleared are cleared. For more information, see
the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to.
15
ALERT
Active High Output. This pin is asserted when there is no SPI activity on the interface pins for a preset time. For
more information, see the Alert Output section.
16
FAULT
Active Low, Open-Drain Output. This pin is asserted low when any of the following conditions is detected:
open circuit in current mode; short circuit in voltage mode; PEC error; or an overtemperature condition (see
the Fault Output section).
17
POC
Power-On Condition. This pin determines the power-on condition and is read during power-on and after a
device reset. If POC = 0, the device is powered up with the voltage and current channels in tristate mode. If
POC = 1, the device is powered up with a 30 kΩ pull-down resistor to ground on the voltage output channel,
and the current channel is in tristate mode.
18
RESET
Hardware Reset, Active Low Input.
19
AVDD
Positive Analog Supply Pin. The voltage range is from 9 V to 33 V.
20
COMPLV_A
Optional Compensation Capacitor Connection for VOUT_A Output Buffer. Connecting a 220 pF capacitor
between this pin and the VOUT_A pin allows the voltage output to drive up to 2 μF. Note that the addition
of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time.
21
VSENSE_A
Sense Connection for the Negative Voltage Output Load Connection for VOUT_A. This pin must stay within
±3.0 V of AGND for specified operation.
22
+VSENSE_A
Sense Connection for the Positive Voltage Output Load Connection for VOUT_A. The difference in voltage
between this pin and the VOUT_A pin is added directly to the headroom requirement.
23
COMPDCDC_A
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC
Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section.
24
VBOOST_A
Supply for Channel A Current Output Stage (see Figure 71). This pin is also the supply for the VOUT_A stage,
which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as
shown in Figure 77.
25
VOUT_A
Buffered Analog Output Voltage for DAC Channel A.
26
IOUT_A
Current Output Pin for DAC Channel A.
27
AVSS
Negative Analog Supply Pin. The voltage range is from 10.8 V to 26.4 V.
28
COMPLV_B
Optional Compensation Capacitor Connection for VOUT_B Output Buffer. Connecting a 220 pF capacitor
between this pin and the VOUT_B pin allows the voltage output to drive up to 2 μF. Note that the addition
of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time.
29
VSENSE_B
Sense Connection for the Negative Voltage Output Load Connection for VOUT_B. This pin must stay within
±3.0 V of AGND for specified operation.
30
+VSENSE_B
Sense Connection for the Positive Voltage Output Load Connection for VOUT_B. The difference in voltage
between this pin and the VOUT_B pin is added directly to the headroom requirement.
31
VOUT_B
Buffered Analog Output Voltage for DAC Channel B.
32
COMPDCDC_B
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC
Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section.
33
IOUT_B
Current Output Pin for DAC Channel B.
34
VBOOST_B
Supply for Channel B Current Output Stage (see Figure 71). This pin is also the supply for the VOUT_B stage,
which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as
shown in Figure 77.
35
AGND
Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V.
36
SWB
Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as
shown in Figure 77.
37
GNDSWB
Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground.
38
GNDSWA
Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground.
39
SWA
Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as
shown in Figure 77.
40
AVSS
Negative Analog Supply Pin. The voltage range is from 10.8 V to 26.4 V.
41
SWD
Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as
shown in Figure 77.
42
GNDSWD
Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground.
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