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參數資料
| 型號： | AD5735ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 36/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC QUAD VOLT CUR 64LFCSP |
| 標準包裝： | 750 |
| 設置時間： | 18µs |
| 位數： | 12 |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 4 |
| 電壓電源： | 模擬和數字，雙 ± |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 4 電流，4 電壓 |
| 采樣率（每秒）： | * |
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Data Sheet
AD5735
Rev. C | Page 41 of 48
DIGITAL SLEW RATE CONTROL
The digital slew rate control feature of the AD5735 allows the
user to control the rate at which the output value changes. This
feature is available on both the current and voltage outputs. With
the slew rate control feature disabled, the output value changes
at a rate limited by the output drive circuitry and the attached
load. To reduce the slew rate, the user can enable the digital slew
rate control feature using the SREN bit of the slew rate control
register (see Table 29).
When slew rate control is enabled, the output, instead of slewing
directly between two values, steps digitally at a rate defined by
the SR_CLOCK and SR_STEP parameters. These parameters
are accessible via the slew rate control register (see Table 29).
SR_CLOCK defines the rate at which the digital slew is
updated; for example, if the selected update rate is 8 kHz,
the output is updated every 125 s.
SR_STEP defines by how much the output value changes
at each update.
Together, these parameters define the rate of change of the
output value. Table 34 and Table 35 list the range of values for
the SR_CLOCK and SR_STEP parameters, respectively.
Table 34. Slew Rate Update Clock Options
SR_CLOCK
Update Clock Frequency1
0000
64 kHz
0001
32 kHz
0010
16 kHz
0011
8 kHz
0100
4 kHz
0101
2 kHz
0110
1 kHz
0111
500 Hz
1000
250 Hz
1001
125 Hz
1010
64 Hz
1011
32 Hz
1100
16 Hz
1101
8 Hz
1110
4 Hz
1111
0.5 Hz
1 These clock frequencies are divided down from the 13 MHz internal
Table 35. Slew Rate Step Size Options
SR_STEP
Step Size (LSB)
000
1
001
2
010
4
011
16
100
32
101
64
110
128
111
256
The following equation describes the slew rate as a function of
the step size, the update clock frequency, and the LSB size.
Size
LSB
Frequency
Clock
Update
Size
Step
Change
Output
Rate
Slew
×
=
where:
Slew Rate is expressed in seconds.
Output Change is expressed in amperes for IOUT_x or in
volts for VOUT_x.
The update clock frequency for any given value is the same for
all output ranges. The step size, however, varies across output
ranges for a given value of step size because the LSB size is
different for each output range.
When the slew rate control feature is enabled, all output changes
occur at the programmed slew rate (see the DC-to-DC Converter
Settling Time section for more information). For example, if the
CLEAR pin is asserted, the output slews to the clear value at the
programmed slew rate (assuming that the channel is enabled to
be cleared).
If more than one channel is enabled for digital slew rate control,
care must be taken when asserting the CLEAR pin. If a channel
under slew rate control is slewing when the CLEAR pin is asserted,
other channels under slew rate control may change directly to
their clear code not under slew rate control.
DYNAMIC POWER CONTROL
When configured in current output mode, the AD5735 provides
integrated dynamic power control using a dc-to-dc boost converter
circuit. This circuit reduces power consumption compared with
standard designs.
In standard current input module designs, the load resistor
values can range from typically 50 to 750 . Output module
systems must source enough voltage to meet the compliance
voltage requirement across the full range of load resistor values.
For example, in a 4 mA to 20 mA loop when driving 20 mA, a
compliance voltage of >15 V is required. When driving 20 mA
into a 50 load, a compliance voltage of only 1 V is required.
The AD5735 circuitry senses the output voltage and regulates
this voltage to meet the compliance requirements plus a small
headroom voltage. The AD5735 is capable of driving up to
24 mA through a 1 k load.
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| AD5737ACPZ | 功能描述:IC DAC QUAD 12BIT CUR 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數:12 數據接口:串行，SPI? 轉換器數目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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| AD5737X | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity |
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