參數(shù)資料
型號(hào)： AD5542ABCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT SRL 16LFCSP
設(shè)計(jì)資源： High Precision Digital-to-Analog Conversion Using the 16-Bit AD5542/1, ADR421, and AD8628 (CN0079)
How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
標(biāo)準(zhǔn)包裝： 1
系列： nanoDAC™
設(shè)置時(shí)間： 1µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 825µW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-WFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類(lèi)型： *
采樣率（每秒）： *
其它名稱(chēng)： AD5542ABCPZ-REEL7DKR
AD5512A/AD5542A
Rev. A | Page 18 of 24
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5512A/AD5542A is via
a serial bus that uses standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 3- or 4-wire interface consisting of a clock
signal, a data signal, and a synchronization signal. The
AD5512A/AD5542A require a 16-bit data-word with data
valid on the rising edge of SCLK. The DAC update can be
done automatically when all the data is clocked in, or it can
be done under the control of the LDAC.
AD5512A/AD5542A TO ADSP-BF531 INTERFACE
The SPI interface of the AD5512A/AD5542A is designed to be
easily connected to industry-standard DSPs and micro-
controllers. Figure 33 shows how the AD5512A/AD5542A
can be connected to the Analog Devices, Inc., Blackfin DSP.
The Blackfin has an integrated SPI port that can be connected
directly to the SPI pins of the AD5512A/AD5542A.
AD5512A/
AD5542A
CS
SCLK
DIN
LDAC
SPISELx
SCK
MOSI
PF9
ADSP-BF531
09199-
044
Figure 33. AD5512A/AD5542A to ADSP-BF531 Interface
AD5512A/AD5542A TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 34 shows how one SPORT interface can be used to
control the AD5512A/AD5542A.
09919-
045
AD5512A/
AD5542A
CS
SCLK
DIN
LDAC
SPORT_TFS
SPORT_TSCK
SPORT_DTO
GPIO0
ADSP-BF527
Figure 34. AD5512A/AD5542A to ADSP-BF527 Interface
AD5512A/AD5542A TO 68HC11/68L11 INTERFACE
Figure 35 shows a serial interface between the AD5512A/
AD5542A and the 68HC11/68L11 microcontroller. SCK of
the 68HC11/68L11 drives the SCLK of the DAC, and the
MOSI output drives the serial data line serial DIN. The CS
signal is driven from one of the port lines. The 68HC11/68L11 is
configured for master mode: MSTR = 1, CPOL = 0, and CPHA =
0. Data appearing on the MOSI output is valid on the rising
edge of SCK.
LDAC
CS
DIN
SCLK
PC6
PC7
MOSI
SCK
AD5512A/
AD5542A*
68HC11/
68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
09199-
026
Figure 35. AD5512A/AD5542A to 68HC11/68L11 Interface
AD5512A/AD5542A TO ADSP-2101 INTERFACE
Figure 36 shows a serial interface between the AD5512A/
AD5542A and the ADSP-2101. The ADSP-2101 should be
set to operate in the SPORT transmit alternate framing mode.
The ADSP-2101 is programmed through the SPORT control
register and should be configured as follows: internal clock
operation, active low framing, 16-bit word length. Transmission
is initiated by writing a word to the Tx register after the SPORT
has been enabled. As the data is clocked out on each rising edge
of the serial clock, an inverter is required between the DSP and
the DAC, because the AD5512A/AD5542A clock data in on the
falling edge of the SCLK.
LDAC
CS
DIN
SCLK
FO
TFS
DT
SCLK
AD5512A/
AD5542A*
ADSP-2101
*ADDITIONAL PINS OMITTED FOR CLARITY.
09199-
025
Figure 36. AD5512A/AD5542A to ADSP-2101 Interface
AD5512A/AD5542A TO MICROWIRE INTERFACE
Figure 37 shows an interface between the AD5512A/AD5542A
and any MICROWIRE-compatible device. Serial data is shifted
out on the falling edge of the serial clock and into the AD5512A/
AD5542A on the rising edge of the serial clock. No glue logic
is required because the DAC clocks data into the input shift
register on the rising edge.
DIN
SCLK
SO
SCLK
AD5512A/
AD5542A*
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY.
CS
09199-
027
Figure 37. AD5512A/AD5542A to MICROWIRE Interface
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