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參數(shù)資料
| 型號(hào)： | A48P4616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 330PF 50V CERAMIC MONO 5% |
| 中文描述： | 16米x 16位DDR內(nèi)存 |
| 文件頁(yè)數(shù)： | 15/71頁(yè) |
| 文件大?。?/td> | 2068K |
| 代理商： | A48P4616 |
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A48P4616
Preliminary (September, 2005, Version 0.0)
14
AMIC Technology, Corp.
As a means to specify whether a DDR SDRAM device
supports the t
RAS
lockout feature, a new parameter has been
defined, t
RAP
(RAS Command to Read Command with Auto
Precharge or better stated Bank Activate to Read Command
with Auto Precharge). For devices that support the t
RAS
lockout feature, t
RAP
= t
RCD(min)
. This allows any Read
Command (with or without Auto Precharge) to be issued to
an open bank once t
RCD(min)
is satisfied.
Burst Terminate
The Burst Terminate command is used to truncate read
bursts (with Auto Precharge disabled). The most re-cently
registered Read command prior to the Burst Terminate
command is truncated, as shown in the Operation section of
this data sheet. Write burst cycles are not to be terminated
with the Burst Terminate command.
Auto Refresh
Auto Refresh is used during normal operation of the DDR
SDRAM and is analogous to CAS Before RAS (CBR)
Refresh in previous DRAM types. This command is
nonpersistent, so it must be issued each time a refresh is
required.
The refresh addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an Auto Refresh command. The 256Mb DDR SDRAM
requires Auto Refresh cycles at an average periodic interval
of 7.8
s (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the
DDR SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR SDRAM
retains data without external clocking. The Self Refresh
command is initiated as an Auto Refresh command
coincident with CKE transitioning low. The DLL is
automatically disabled upon entering Self Refresh, and is
automatically enabled upon exiting Self Refresh (200 clock
cycles must then occur before a Read command can be
issued). Input signals except CKE (low) are “Don’t Care”
during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of
commands. CK (and CK) must be stable prior to CKE
returning high. Once CKE is high, the SDRAM must have
NOP commands issued for t
XSNR
because time is required
for the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before
applying any other command.
tRAP Definition
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