參數(shù)資料
型號： A48P4616
廠商： AMIC Technology Corporation
英文描述： CAP 330PF 50V CERAMIC MONO 5%
中文描述： 16米x 16位DDR內(nèi)存
文件頁數(shù)： 12/71頁
文件大?。?/td> 2068K
代理商： A48P4616
A48P4616
Preliminary (September, 2005, Version 0.0)
11
AMIC Technology, Corp.
Extended Mode Register
The Extended Mode Register controls functions beyond
those controlled by the Mode Register; these additional
functions include DLL enable/disable, bit A0; output drive
strength selection, bit A1; and QFC output enable/disable, bit
A2 (NTC optional). These functions are controlled via the bit
settings shown in the Extended Mode Register Definition.
The Extended Mode Register is programmed via the Mode
Register Set command (with BA0 = 1 and BA1 = 0) and
retains the stored information until it is programmed again or
the device loses power. The Extended Mode Register must
be loaded when all banks are idle, and the controller must
wait the specified time before initiating any subsequent
operation. Violating either of these requirements result in
unspecified operation.
QFC Enable/Disable
The QFC signal is an optional DRAM output control used to
isolate module loads (DIMMs) from the system memory bus
by means of external FET switches when the given module
(DIMM) is not being accessed. The QFC function is an
optional feature for NANYA and is not included on all DDR
SDRAM devices.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable
is required during power up initialization, and upon returning
to normal operation after having disabled the DLL for the
purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is
automatically re-enabled upon exit of self refresh operation.
Any time the DLL is enabled, 200 clock cycles must occur to
allow time for the internal clock to lock to the externally
applied clock before a Read command can be issued. This is
the reason for introducing timing parameter t
XSRD
for DDR
SDRAM’s (Exit Self Refresh to Read Command). Non- Read
commands can be issued 2 clocks after the DLL is enabled
via the EMRS command (t
MRD
) or 10 clocks after the DLL is
enabled via self refresh exit command (t
XSNR
, Exit Self
Refresh to Non-Read Command).
Output Drive Strength
The normal drive strength for all outputs is specified to be
SSTL_2, Class II.
Extended Mode Register Definition
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0*
1*
Operating Mode
QFC
DS
DLL
Extended
Mode Register
Operating Mode
A2
QFC
Drive Strength
A0
DLL
A12-A3
0
A2-A0
Valid
Type
0
1
Disable
A1
0
Type
Normal
0
1
Enable
Disable
Normal Operation
All Other States
Reserved
Enable (Optional)
-
-
1
Reserved
Note:
*
BA0 and BA1 must be 1, 0 to select the Extended Mode Register
(vs. the base Mode Register)
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