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參數(shù)資料
| 型號： | A43E06321G-75F |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | General Purpose |
| 中文描述： | 為512k × 32位× 2銀行低功耗同步DRAM |
| 文件頁數(shù)： | 21/46頁 |
| 文件大小： | 1351K |
| 代理商： | A43E06321G-75F |
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A43E06321
PRELIMINARY (July, 2005, Version 0.0)
20
AMIC Technology, Corp.
12. About Burst Type Control
Sequential counting
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
Basic
MODE
Interleave counting
Random
MODE
Random column Access
t
CCD
= 1 CLK
13. About Burst Length Control
1
At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “010”
At MRS A2,1,0 = “011”.
At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
t
RDL
= 2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
During read/write burst with auto precharge, RASinterrupt cannot be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge,
CAS
interrupt can not be issued.
2
4
8
Basic
MODE
Special
MODE
BRSW
RASInterrupt
(Interrupted by Precharge)
Interrupt
MODE
CAS
Interrupt
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A43E06321G-75UF | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95F | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95UF | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321 | Knob, Accessories; Color:Red; External Height:0.27" RoHS Compliant: Yes |
| A43E16161 | 1M X 16 Bit X 2 Banks Low Power Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A43E06321G-75UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E0632G-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43E0632G-95I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
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