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參數(shù)資料
| 型號(hào)： | A43E06161V-95F |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 16 Bit X 2 Banks Synchronous DRAM |
| 中文描述： | 為512k × 16位× 2銀行同步DRAM |
| 文件頁(yè)數(shù)： | 6/46頁(yè) |
| 文件大?。?/td> | 1289K |
| 代理商： | A43E06161V-95F |
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A43E06161
PRELIMINARY
(July, 2005, Version 0.1)
5
AMIC Technology, Corp.
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
C
DC1
0.1 + 0.01
μ
F
Decoupling Capacitance between VDDQ and VSSQ
C
DC2
0.1 + 0.01
μ
F
Note:
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C or -40oC to +85oC)
Speed
Symbol
Parameter
Test Conditions
CAS
Latency
-75
-95
Unit
Notes
I
cc1
Operating Current
(One Bank Active)
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min
)
, I
OL
= 0mA
20
mA
1
I
cc2
P
CKE
≤
V
IL
(max), t
CC
= 15ns
0.3
I
cc2
PS
Precharge Standby
Current in power-
down mode
CKL
≤
VIL(max), t
CC
=
∞
0.1
mA
I
CC2
N
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
5
I
CC2
NS
Precharge Standby
Current in non
power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable.
2
mA
I
CC3
P
Active Standby
Current in power-
down mode
CKE
≤
V
IL
(max), t
CC
= 15ns
2
mA
I
CC3
N
Active Standby
current in non
power-down mode
(One Bank Active)
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
10
mA
I
CC4
Operating Current
(Burst Mode)
I
OL
= 0mA, Page Burst
All bank Activated, t
CCD
= t
CCD
(min)
20
mA
1
I
CC5
Refresh Current
t
RC
≥
t
RC
(min)
20
mA
2
I
CC6
Self Refresh
Current
Deep Power Down
Current
CKE
≤
0.2V
200
μ
A
I
CC7
CKE
≤
0.2V
10
μ
A
Note:
1. Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2. Refresh period is 32ms. Addresses are changed only one time during t
CC
(min).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A43E06161V-95U | 512K X 16 Bit X 2 Banks Synchronous DRAM |
| A43E06161V-95UF | 512K X 16 Bit X 2 Banks Synchronous DRAM |
| A43E06321G-75F | General Purpose |
| A43E06321G-75UF | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95F | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A43E06161V-95U | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:512K X 16 Bit X 2 Banks Synchronous DRAM |
| A43E06161V-95UF | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:512K X 16 Bit X 2 Banks Synchronous DRAM |
| A43E0616G-75I | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43E0616G-95I | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43E0616V-75I | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
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