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參數(shù)資料
| 型號(hào)： | A43E06161V-95F |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 16 Bit X 2 Banks Synchronous DRAM |
| 中文描述： | 為512k × 16位× 2銀行同步DRAM |
| 文件頁數(shù)： | 14/46頁 |
| 文件大?。?/td> | 1289K |
| 代理商： | A43E06161V-95F |
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A43E06161
PRELIMINARY (July, 2005, Version 0.1)
13
AMIC Technology, Corp.
by “t
RC
(min)”. The minimum number of clock cycles required
can be calculated by driving “t
RC
” with clock cycle time and
then rounding up to the next higher integer. The auto refresh
command must be followed by NOP’s until the auto refresh
operation is completed. Both banks will be in the idle state at
the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or a burst of 2048 auto refresh
cycles once in 32ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on
CS
,
RAS
,
CAS
and CKE with high on
WE
. Once the self refresh mode is entered, only CKE state
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP’s
for a minimum time of “t
RC
” before the SDRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to used
burst 2048 auto refresh cycles immediately after exiting self
refresh.
Deep Power Down Mode
The Deep Power Down Mode is an unique function on Low
Power SDRAMs with very low standby currents. All internal
voltage generators inside the Low Power SDRAMs are
stopped and all memory data will be lost in this mode. To
enter the Deep Power Down Mode all banks must be
precharged and the necessary Precharged Delay t
RP
must
occur.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A43E06161V-95U | 512K X 16 Bit X 2 Banks Synchronous DRAM |
| A43E06161V-95UF | 512K X 16 Bit X 2 Banks Synchronous DRAM |
| A43E06321G-75F | General Purpose |
| A43E06321G-75UF | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95F | 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A43E06161V-95U | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 16 Bit X 2 Banks Synchronous DRAM |
| A43E06161V-95UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 16 Bit X 2 Banks Synchronous DRAM |
| A43E0616G-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43E0616G-95I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
| A43E0616V-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
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