參數(shù)資料
型號： A3PE1500-PQG208
元件分類： FPGA
英文描述： FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封裝： 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 61/152頁
文件大?。?/td> 4932K
代理商： A3PE1500-PQG208
ProASIC3E DC and Switching Characteristics
2- 4
v1.2
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper
power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLXL exceed
brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1
on page 2-4 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±
0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the
Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information
on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
Figure 2-1 I/O State as a Function of VCCI and VCC Voltage Levels
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because V
CCI
/V
CC
are below
specification. For the same reason, input
buffers do not meet V
IH
/V
IL
levels, and
output buffers do not meet V
OH
/V
OL
levels.
Min V
CCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Activation trip point:
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, V
IH
/V
IL
, V
OH
/V
OL
, etc.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential
but slower because V
CCI is
below specification. For the
same reason, input buffers do not
meet V
IH
/V
IL
levels, and output
buffers do not meet V
OH
/V
OL
levels.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCI
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the V
CC
is below specification.
V
CC = VCCI + VT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PE1500-PQG208I 功能描述:IC FPGA 1KB FLASH 1.5M 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A3PE1500-PQG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE1500-PQG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE1500-PQG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE1500-PQG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
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