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參數(shù)資料
| 型號： | A3PE1500-PQG208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 38400 CLBS, 1500000 GATES, PQFP208 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 148/152頁 |
| 文件大小： | 4932K |
| 代理商： | A3PE1500-PQG208 |
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ProASIC3E DC and Switching Characteristics
v1.2
2 - 83
Part Number and Revision Date
Part Number 51700098-002-2
Revised June 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (v1.2)
Page
v1.1
(January 2008)
The title of Table 2-4 Overshoot and Undershoot Limits 1 was modified to
remove "as measured on quiet I/Os." Table note 2 was revised to remove
"estimated SSO density over cycles." Table note 3 was deleted
.
updated.
v1.0
(January 2008)
Temperature 1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
The "PLL Behavior at Brownout Condition" section is new.
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
was incorrect. It previously said TJ and it was corrected and changed to TA.
In Table 2-94 ProASIC3E CCC/PLL Specification, the SCLK parameter and note
1 are new.
Table 2-99 JTAG 1532 was populated with the parameter data, which was not
in the previous version of the document.
v2.1
(July 2007)
This document was previously in datasheet v2.1. As a result of moving to the
handbook format, Actel has restarted the version numbers so the new version
number is v1.0.
N/A
v2.0
(April 2007)
The caption "Main (chip)" in Figure 2-9 Overview of Automotive ProASIC3
VersaNet Global Network was changed to "Chip (main)."
2-9
The TJ parameter in Table 3-2 Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added.
3-2
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
2-15
Advance v0.6
(January 2007)
The "PLL Macro" section was updated to include power-up information.
2-15
Table 2-13 ProASIC3E CCC/PLL Specification was updated.
2-30
Figure 2-19 Peak-to-Peak Jitter Definition is new.
2-18
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
2-21
The "RESET" section was updated with read and write information.
2-25
The "RESET" section was updated with read and write information.
2-25
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
2-28
In the Table 2-15 Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
2-34
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3PE1500-PQG208I | 功能描述:IC FPGA 1KB FLASH 1.5M 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A3PE1500-PQG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE1500-PQG896ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE1500-PQG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE1500-PQG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
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