參數(shù)資料
型號: A3PE1500-PQG208
元件分類: FPGA
英文描述: FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù): 120/152頁
文件大小: 4932K
代理商: A3PE1500-PQG208
ProASIC3E Flash Family FPGAs
v1.1
1 - 3
Advanced Architecture
The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Pro I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the ProASIC3E core tile as either a three-input
lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the
FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation
architecture Flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.
Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable
interconnect programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)
programming of ProASIC3E devices via an IEEE 1532 JTAG interface.
Figure 1-1 ProASIC3E Device Architecture Overview
4,608-Bit Dual-Port SRAM
or FIFO Block
VersaTile
RAM Block
CCC
Pro I/Os
ISP AES Decryption
User Nonvolatile
FlashROM
Charge Pumps
4,608-Bit Dual-Port SRAM
or FIFO Block
RAM Block
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