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| 型號(hào)： | A3PE-STARTER-KIT-2 |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 2/162頁(yè) |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR A3PE1500 PROASIC3 |
| 產(chǎn)品變化通告： | Kit/Part Number Change 25/Jul/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProASIC3 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | A3PE1500 |
| 所含物品： | 板，電源，編程器 |
| 其它名稱： | 1100-1144 A3PE-STARTER-KIT |
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ProASIC3E Device Family Overview
1-4
Revision 13
VersaTiles
The ProASIC3E core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS core
tiles. The ProASIC3E VersaTile supports the following:
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-2 for VersaTile configurations.
User Nonvolatile FlashROM
ProASIC3E devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can
be used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard ProASIC3E IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks, as in security keys stored in the FlashROM for a
user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The ProASIC3E development software solutions, Libero System-on-Chip (SoC) and Designer, have
extensive support for the FlashROM. One such feature is auto-generation of sequential programming
files for applications requiring a unique serial number in each part. Another feature allows the inclusion of
static data for system version control. Data for the FlashROM can be generated quickly and easily using
Libero SoC and Designer software tools. Comprehensive programming file support is also included to
allow for easy programming of large numbers of parts with differing FlashROM contents.
Figure 1-2 VersaTile Configurations
X1
Y
X2
X3
LUT-3
Data
Y
CLK
Enable
CLR
D-FF
Data
Y
CLK
CLR
D-FF
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3PFA1X201J1 | 制造商:APEM 功能描述:Pushbutton,A3,latching,12V,red |
| A3PFA1X201J2 | 制造商:APEM 功能描述:Pushbutton,latching,12V,green |
| A3PFA1X201J3 | 制造商:APEM 功能描述:Pushbutton,latching,12V,amber |
| A3PFA1X201J4 | 制造商:APEM 功能描述:Pushbutton,A3,latching,12V,blue |
| A3PFA1X201K1 | 制造商:APEM 功能描述:Pushbutton,A3,latching 24V,red |
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