- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄294784 > A1415A-PL84C FPGA, 200 CLBS, 1500 GATES, 125 MHz, PQCC84 PDF資料下載
參數(shù)資料
| 型號： | A1415A-PL84C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 200 CLBS, 1500 GATES, 125 MHz, PQCC84 |
| 封裝： | PLASTIC, MS-007-AE, LCC-84 |
| 文件頁數(shù)： | 67/68頁 |
| 文件大?。?/td> | 489K |
| 代理商： | A1415A-PL84C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當(dāng)前第67頁第68頁
1-182
The S-module contains a full implementation of the C-module
plus a clearable sequential element that can either
implement a latch or flip-flop function. The S-module can
therefore implement any function implemented by the
C-module. This allows complex combinatorial-sequential
functions to be implemented with no delay penalty. The
Designer Series Development System will automatically
combine any C-module macro driving an S-module macro into
the S-module, thereby freeing up a logic module and
eliminating a module delay.
The clear input CLR is accessible from the routing channel.
In addition, the clock input may be connected to one of three
clock networks: CLKA, CLKB, or HCLK. The C-module and
S-module functional descriptions are shown in Figures 2
and 3. The clock selection is determined by a multiplexor
select at the clock input to the S-module.
I/Os
I/O Modules
I/O modules provide an interface between the array and the
I/O Pad Drivers. I/O modules are located in the array and
access the routing channels in a similar fashion to logic
modules. The I/O module schematic is shown in Figure 4. The
signals DataIn and DataOut connect to the I/O pad driver.
Each I/O module contains two D-type flip-flops. Each flip-flop
is connected to the dedicated I/O clock (IOCLK). Each
flip-flop can be bypassed by nonsequential I/Os. In addition,
each flip-flop contains a data enable input that can be
accessed from the routing channels (ODE and IDE). The
asynchronous preset/clear input is driven by the dedicated
preset/clear network (IOPCL). Either preset or clear can be
selected individually on an I/O module by I/O module basis.
The I/O module output Y is used to bring Pad signals into the
array or to feed the output register back into the array. This
allows the output register to be used in high-speed state
machine applications. Side I/O modules have a dedicated
output segment for Y extending into the routing channels
above and below (similar to logic modules). Top/Bottom I/O
modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses
and LVTs (F-fuses and LVTs are explained in detail in the
routing section).
Figure 2 C-Module Diagram
D11
D01
D00
D10
A1 B1
A0 B0
Y
OUT
S1
S0
Figure 3 S-Module Diagram
CLR
CLK
D11
D01
D00
D10
A1 B1
A0 B0
Y
Q
D
OUT
S0
S1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A1415A-PLG84C | FPGA, 200 CLBS, 1500 GATES, 125 MHz, PQCC84 |
| A1415A-PQ100C | FPGA, 200 CLBS, 1500 GATES, 125 MHz, PQFP100 |
| A1415A-PQG100C | FPGA, 200 CLBS, 1500 GATES, 125 MHz, PQFP100 |
| A1415A-VQ100C | FPGA, 200 CLBS, 1500 GATES, 125 MHz, PQFP100 |
| A1415A-VQG100C | FPGA, 200 CLBS, 1500 GATES, 125 MHz, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1415A-PL84I | 功能描述:IC FPGA 1500 GATES 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A1415A-PL84M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 1.5K Gates 200 Cells 125MHz 0.8um Technology 5V 84-Pin PLCC 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 125MHZ 0.8UM 5V 84PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 1500 GATES 84-PLCC MIL |
| A1415A-PLG84C | 功能描述:IC FPGA 1500 GATES 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A1415A-PLG84I | 功能描述:IC FPGA 1500 GATES 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A1415A-PLG84M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 1.5K Gates 200 Cells 125MHz 0.8um (CMOS) Technology 5V 84-Pin PLCC 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 125MHZ 0.8UM 5V 84PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 1500 GATES 84-PLCC MIL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。