參數(shù)資料
型號： 9S12XDP512DGV1
英文描述： Device User Guide for Mask Set 0L40V ( First Silicon)
中文描述： 設(shè)備用戶指南掩模組0L40V（第一硅）
文件頁數(shù)： 100/152頁
文件大小： 1231K
代理商： 9S12XDP512DGV1
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
100
Section 14 Oscillator (OSC_LCP) Block
Consult the OSC_LCP Block Guide for information about the Oscillator Module.
Section 15 Clock and Reset Generator (CRG) Block
Description
The COP timeout rate bits CR[2:0] in the COPCTL register are loaded on rising edge of
RESET
from
the Flash Control Register FCTL ($0107) located in the Flash EEPROM block.See
Table 15-1
. On
RESET
intospecialmodestheCOPtimeoutratebitsarealwayssettothehighestwatchdograte.(CR[2:0]
= 111, 2
24
oscillator cycles to time-out)
Table 15-1
shows also the write restrictions of the COP rate bits
CR[2:0]intheCOPCTLregister.WritingtotheMODERegisterintheS12XEBIhasnoeffectontheCOP
rate bits in the COPCTL register.
The FCTL register is loaded from the Flash Configuration Field byte at global address $7F_FF0E during
the reset sequence. For more information on FCTL register refer to the FTX512K4 Block Guide.
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
Section 16 Enhanced Capture Timer (ECT) Block
Table 15-1 Initial COP Configuration
NV[2:0] in
FCTL
Register
CR[2:0] in COPCTL
Register
Write of CR[2:0]
(afterresetinitializiationfrom
FCTL)
Normal &
Emulation Modes
Special
Modes
Normal &
Emulatin Modes
Special
Modes
000
111
111
never
always
001
110
010
101
011
100
100
011
101
010
110
001
111
000
000
once
F
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
9S12XDP512DGV2 Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9S12XDP512DGV2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
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