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Central Processing Unit (CPU)
MC9S12T64Revision 1.1.1
50
Central Processing Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
TBEQ
abdxysp
,
rel9
Test and branch if equal to 0
If (counter)=0, then (PC)
+
2
+
rel
PC
Tablelookupandinterpolate, 8-bit
(M)+[(B)
×
((M+1)–(M))]
A
Testandbranchifnot equal to 0
If (counter)
≠
0, then (PC)
+
2
+
rel
PC
Transfer from registertoregister
(r1)
r2r1andr2samesize
$00:(r1)
r2r1=8-bit;r2=16-bit
(r1
L
)
r2r1=16-bit;r2=8-bit
TransferCCRtoA; (CCR)
A
REL
(9-bit)
IDX
04 lb rr
PPP
(branch)
PPO
(no branch)
TBL
oprx0_xysppc
18 3D xb
ORfffP
TBNE
abdxysp
,
rel9
REL
(9-bit)
INH
04 lb rr
PPP
(branch)
PPO
(no branch)
TFR
abcdxysp
,
abcdxysp
B7 eb
P
or
TPASame as TFRCCR,A
INH
B7 20
P
TRAP
trapnum
Trapunimplementedopcode;
(SP)–2
SP
RTN
H
:RTN
L
M
SP
:M
SP+1
(SP)–2
SP; (Y
H
:Y
L
)
M
SP
:M
SP+1
(SP)–2
SP; (X
H
:X
L
)
M
SP
:M
SP+1
(SP)–2
SP; (B:A)
M
SP
:M
SP+1
(SP)–1
SP; (CCR)
M
SP
1
I; (trap vector)
PC
TestM; (M)–0
INH
18 tn
tn = $30–$39
or
tn = $40–$FF
OVSPSSPSsP
TST
opr16a
TST
oprx0_xysppc
TST
oprx9
,
xysppc
TST
oprx16
,
xysppc
TST[D,
xysppc
]
TST[
oprx16
,
xysppc
]
TSTA
TSTB
TSXSame as TFRSP,X
TestA;(A)–0
TestB;(B)–0
TransferSPtoX;(SP)
X
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
INH
F7 hh ll
E7 xb
E7 xb ff
E7 xb ee ff
E7 xb
E7 xb ee ff
97
D7
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
O
O
B7 75
P
TSYSame asTFRSP,Y
TransferSPtoY;(SP)
Y
INH
B7 76
P
TXSSame asTFRX,SP
TransferXtoSP;(X)
SP
INH
B7 57
P
TYSSame asTFRY,SP
TransferYtoSP;(Y)
SP
INH
B7 67
P
WAI
Wait for interrupt; (SP)–2
SP
RTN
H
:RTN
L
M
SP
:M
SP+1
(SP)–2
SP; (Y
H
:Y
L
)
M
SP
:M
SP+1
(SP)–2
SP; (X
H
:X
L
)
M
SP
:M
SP+1
(SP)–2
SP; (B:A)
M
SP
:M
SP+1
(SP)–1
SP; (CCR)
M
SP
INH
3E
OSSSSsf
(before interrupt)
fVfPPP
(after interrupt)
or
or
WAV
Calculate
weighted
average; sum of
products (SOP)
and sum of
weights (SOW)*
Special
18 3C
Of(frr^ffff)O**
SSS+UUUrr^***
*InitializeB,X,andY:B=numberofelements;XpointsatfirstelementinS
i
list;YpointsatfirstelementinF
i
list.AllS
i
andF
i
elementsare8-bit values.
**The
frr^ffff
sequenceistheloopforoneiterationofSOPandSOWaccumulation. The
^
denotes a check for pending interrupt requests.
***Additional cycles caused by an interrupt:
SSS
is the exit sequence and
UUUrr^
is the re-entry sequence. Intermediate values use six stack bytes.
wavr*
ResumeexecutinginterruptedWAV
Special
3C
UUUrr^ffff(frr^
ffff)O**
SSS+UUUrr^***
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Mode
Machine
Coding (Hex)
Access Detail
S X H I N Z V C
– – – – – – – –
– – – –
–
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – 1 – – – –
– – – –
0 0
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – 1 – – – –
– 1 – 1 – – – –
F
i
i
1
=
B
∑
X
S
i
F
i
i
1
=
B
∑
Y:D
– – –
– – –
F
Freescale Semiconductor, Inc.
n
.