參數(shù)資料
型號(hào)： 9LPRS480YKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PQCC64
封裝： ROHS COMPLIANT, PLASTIC, MLF-64
文件頁數(shù)： 15/25頁
文件大?。?/td> 249K
代理商： 9LPRS480YKLFT
22
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
1391D—02/02/09
SMBus Table: CLKREQ# Configuration Register
Byte
22
Name
Control Function
Type
0
1
Default
Bit 7
CPU/HTT/SRC/ATIG M/N En
CPU/HTT/SRC/ATIG PLL
M/N Prog. Enable
RW
M/N Prog. Disabled
M/N Prog. Enabled
0
Bit 6
SB_SRC M/N En
SB_SRC M/N Prog. Enable
RW
M/N Prog. Disabled
M/N Prog. Enabled
0
Bit 5
Reserved
RW
-
0
Bit 4
Reserved
RW
-
0
Bit 3
Reserved
RW
-
0
Bit 2
Reserved
RW
-
X
Bit 1
Reserved
RW
-
X
Bit 0
Reserved
RW
-
X
SMBus Table: CLKREQ# Configuration Register
Byte
23
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
RW
-
0
Bit 6
Reserved
RW
-
0
Bit 5
Reserved
RW
-
0
Bit 4
CLKREQ4#_Enable
CLKREQ4# controls SRC4
RW
Not Controlled
Controlled
0
Bit 3
CLKREQ3#_Enable
CLKREQ3# controls SRC3
RW
Not Controlled
Controlled
0
Bit 2
CLKREQ2#_Enable
CLKREQ2# controls SRC2
RW
Not Controlled
Controlled
0
Bit 1
CLKREQ1#_Enable
CLKREQ1# controls SRC1
RW
Not Controlled
Controlled
0
Bit 0
CLKREQ0#_Enable
CLKREQ0# controls SRC0
RW
Not Controlled
Controlled
0
SMBus Table: Test Mode Configuration Register
Byte
24
Name
Control Function
Type
0
1
Default
Bit 7
Test_Md_Sel
Selects Test Mode
RW
Normal mode
All ouputs are REF/N
0
Bit 6
DIAG Enable#
DIAG enable
CPU and LCD PLL
RW
Reset forces
B24[6:4,2,0]
to 0
DIAG mode Enabled
0
Bit 5
CPU PLL_LOCK signal
CPU PLL Lock Detect
R
unlocked
Locked
HW
Bit 4
27MHz PLL_LOCK signal
27MHz PLL Lock Detect
R
unlocked
Locked
HW
Bit 3
Fixed PLL_LOCK signal
Fixed PLL Lock Detect
R
unlocked
Locked
HW
Bit 2
SRC PLL_LOCK signal
Fixed PLL Lock Detect
R
unlocked
Locked
HW
Bit 1
Frequency Check
Primary PLL or external
crystal Frequency Accuracy
R
Not Accurate
Accurate
HW
Bit 0
PWRGD Status
Power on Reset Status
R
Invalid voltage levels on
any of the VDDs.
CKPWRGD is not
asserted or external
XTAL not detected.
Valid voltage levels
exist on all the VDD.
CKPWRGD is asserted
and external XTAL is
detected.
HW
SMBus Table:Slew Rate Select Register
Byte
25
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
RW
-
0
Bit 6
Reserved
RW
-
0
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
1
RW
REF1_Slew Rate
RW
Slew Rate Control
RW
REF0_Slew Rate
Slew Rate Control
REF2_Slew Rate
Slew Rate Control
These bits program the slew rate of the single
ended outputs. The maximum slew rate is
1.9V/ns and the minimum slew rate is 1.1V/ns.
The slew rate selection is as follows:
11 = 1.9V/ns
10 = 1.6V/ns
01 = 1.1V/ns
00 = tristated
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