參數(shù)資料
型號： 9LPRS480YKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PQCC64
封裝： ROHS COMPLIANT, PLASTIC, MLF-64
文件頁數(shù)： 14/25頁
文件大?。?/td> 249K
代理商： 9LPRS480YKLFT
21
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
1391D—02/02/09
SMBUS Table: SB_SRC Frequency Control Register
Byte
17
Name
Control Function
Type
0
1
Default
Bit 7
N Div10
RW
X
Bit 6
N Div9
RW
X
Bit 5
N Div8
RW
X
Bit 4
N Div7
RW
X
Bit 3
N Div6
RW
X
Bit 2
N Div5
RW
X
Bit 1
N Div4
RW
X
Bit 0
N Div3
RW
X
SMBUS Table: SB_SRC Spread Spectrum Control Register
Byte
18
Name
Control Function
Type
0
1
Default
Bit 7
SSP7
RW
X
Bit 6
SSP6
RW
X
Bit 5
SSP5
RW
X
Bit 4
SSP4
RW
X
Bit 3
SSP3
RW
X
Bit 2
SSP2
RW
X
Bit 1
SSP1
RW
X
Bit 0
SSP0
RW
X
SMBUS Table: SB_SRC Spread Spectrum Control Register
Byte
19
Name
Control Function
Type
0
1
Default
Bit 7
SSP15
RW
X
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
SMBUS Table: SB_SRC Output Divider Control Register
Byte
20
Name
Control Function
Type
0
1
Default
Bit 7
SB_SRC NDiv0
LSB N Divider Programming
RW
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
SB_SRCDiv3
RW
0000:/2 ; 0100:/4
1000:/8 ; 1100:/16
X
Bit 2
SB_SRCDiv2
RW
0001:/3 ; 0101:/6
1001:/12 ; 1101:/24
X
Bit 1
SB_SRCDiv1
RW
0010:/5 ; 0110:/10
1010:/20 ; 1110:/40
X
Bit 0
SB_SRCDiv0
RW
0011:/15 ; 0111:/18
1011:/36 ; 1111:/72
X
SMBus Table: Device ID register
Byte
21
Name
Control Function
Type
0
1
Default
Bit 7
Device ID7
R
0
Bit 6
Device ID6
R
1
Bit 5
Device ID5
R
1
Bit 4
Device ID4
R
1
Bit 3
Device ID3
R
0
Bit 2
Device ID2
R
1
Bit 1
Device ID1
R
1
Bit 0
Device ID0
R
0
76 hex
Reserved
SRC Divider Ratio
Programming Bits
Spread Spectrum
Programming bit(7:0)
SB_SRC M/N programming.
Bytes 18 and 19 set the the SB_SRC spread
pecentages. Please contact ICS for the
appropriate values.
Device ID
Reserved
Spread Spectrum
Programming bit(14:8)
Bytes 18 and 19 set the the SB_SRC spread
pecentages. Please contact ICS for the
appropriate values.
N Divider Programming
Byte16 bit(7:0) and Byte15
bit(7:6)
The decimal representation of M and N Divider in
Byte 16 and 17 configure the SB_SRC VCO
frequency. See M/N Caculation Tables for VCO
frequency formulas.
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