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參數(shù)資料
| 型號(hào)： | 9LPR502YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁(yè)數(shù)： | 6/29頁(yè) |
| 文件大小： | 282K |
| 代理商： | 9LPR502YGLFT |
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IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator
1124D—02/26/09
Advance Information
ICS9LPR502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
14
Datasheet
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0
PCI1
PCI2
PCI3
PCI4
PCI_F5
1.0ns
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
1,2
33.33MHz output no spread
29.99700
30.00300
ns
2
33.33MHz output spread
30.08421
30.23459
ns
2
33.33MHz output no spread
29.49700
30.50300
ns
2
33.33MHz output nominal/spread
29.56617
30.58421
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.55
V
1
V OH @MIN = 1.0 V
-33
mA
1
VOH@MAX = 3.135 V
-33
mA
1
VOL @ MIN = 1.95 V
30
mA
1
VOL @ MAX = 0.4 V
38
mA
1
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Pin to Pin Skew
tskew
VT = 1.5 V
250
ps
2
Intential PCI to PCI delay
tskew
VT = 1.5 V
100
200
ps
2
Duty Cycle
dt1
VT = 1.5 V
45
55
%
2
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
ps
2
Tabs
Absolute min/max period
Output High Current
IOH
Output Low Current
IOL
Clock period
Tperiod
Electrical Characteristics - USB48MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
2,4
Clock period
Tperiod
48.00MHz output nominal
20.83125
20.83542
ns
2,3
Absolute min/max period
Tabs
48.00MHz output nominal
20.48125
21.18542
ns
2
CLK High Time
THIGH
8.216563
11.15198
V
CLK Low time
TLOW
7.816563
10.95198
V
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.55
V
V OH @MIN = 1.0 V
-29
mA
VOH@MAX = 3.135 V
-23
mA
VOL @ MIN = 1.95 V
29
mA
VOL @ MAX = 0.4 V
27
mA
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
2
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
2
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
2
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
350
ps
2
Output High Current
IOH
Output Low Current
IOL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9LPR502YKLFT | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR |
| 9LPR515CGLF | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購(gòu) 標(biāo)準(zhǔn)包裝:1 |
| 9LPR515CGLFT | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購(gòu) 標(biāo)準(zhǔn)包裝:1,000 |
| 9LPR515CKLF | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購(gòu) 標(biāo)準(zhǔn)包裝:1 |
| 9LPR515CKLFT | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購(gòu) 標(biāo)準(zhǔn)包裝:1,000 |
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