參數(shù)資料
型號： 9LPR502YGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁數(shù)： 23/29頁
文件大?。?/td> 282K
代理商： 9LPR502YGLFT
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator
1124D—02/26/09
Advance Information
ICS9LPR502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
3
Datasheet
SSOP/TSSOP Pin Description (continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
17
SRCT1/SE1
OUT
True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100
MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
18
SRCC1/SE2
OUT
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default
is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
19
GND
PWR
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
20
VDDPLL3_IO
PWR
Power supply for PLL3 output. 1.05 to 3.3V +/-5%.
21
SRCT2/SATAT
OUT
True clock of differential SRC/SATA clock pair.
22
SRCC2/SATAC
OUT
Complement clock of differential SRC/SATA clock pair.
23
GNDSRC
PWR
Ground pin for SRC clocks.
24
SRCT3/CR#_C
I/O
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin,
the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3
output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or
pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
25
SRCC3/CR#_D
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or
SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin,
the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3
output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or
pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
26
VDDSRC_IO
PWR
Power supply for SRC clocks. 1.05 to 3.3V +/-5%.
27
SRCT4
I/O
True clock of differential SRC clock pair 4
28
SRCC4
I/O
Complement clock of differential SRC clock pair 4
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9LPR502YKLFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
9LPR515CGLF 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1
9LPR515CGLFT 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1,000
9LPR515CKLF 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1
9LPR515CKLFT 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1,000
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