- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25569 > 9LPR502YGLFT (INTEGRATED DEVICE TECHNOLOGY INC) SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 PDF資料下載
參數(shù)資料
| 型號： | 9LPR502YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 5/29頁 |
| 文件大小： | 282K |
| 代理商： | 9LPR502YGLFT |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator
1124D—02/26/09
Advance Information
ICS9LPR502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
13
Datasheet
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
Rising Edge Slew Rate
tSLR
Averaging on
2.5
4
V/ns
2, 3
Falling Edge Slew Rate
tFLR
Averaging on
2.5
4
V/ns
2, 3
Slew Rate Variation
tSLVAR
Averaging on
20
%
1, 10
Differential Voltage Swing
VSWING
Averaging off
300
mV
2
Crossing Point Voltage
VXABS
Averaging off
300
550
mV
1,4,5
Crossing Point Variation
VXABSVAR
Averaging off
140
mV
1,4,9
Maximum Output Voltage
VHIGH
Averaging off
1150
mV
1,7
Minimum Output Voltage
VLOW
Averaging off
-300
mV
1,8
Duty Cycle
DCYC
Averaging on
45
55
%
2
CPU Skew
CPUSKEW
Averaging on
100
ps
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1
SRC[10:0] Skew
SRCSKEW
Differential Measurement
3000
ps
1,6,11
1Measurement taken for single ended waveform on a component test board (not in system)
2 Measurement taken from differential waveform on a component test board. (not in system)
3 Slew rate emastured through V_swing voltage range centered about differential zero
4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.
7 The max voltage including overshoot.
8 The min voltage including undershoot.
10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets
C
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
11 For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.
9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced
CC
5 Only applies to the differential rising edge (Clock rising, Clock# falling)
Clock Jitter Specs - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
CPU Jitter - Cycle to Cycle
CPUJC2C
Differential Measurement
85
ps
1
SRC Jitter - Cycle to Cycle
SRCJC2C
Differential Measurement
125
ps
1,2
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential Measurement
250
ps
1
1JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be
somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece
2 Phase jitter requirement: The deisgnated Ge2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed on a componnet
test board under quiet condittions with all outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG or equivalent. Measurement methodology is as defined
by the PCI SIG.
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9LPRS365BKLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 9LPRS365BGLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64 |
| 9LPRS436CKLF | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC48 |
| 9LPRS436CGLF | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 9LPRS436CKLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9LPR502YKLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR |
| 9LPR515CGLF | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1 |
| 9LPR515CGLFT | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1,000 |
| 9LPR515CKLF | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1 |
| 9LPR515CKLFT | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1,000 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。