參數(shù)資料
型號： 9E4101YFILFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PDSO56
封裝： 0.300 INCH, 0.250 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁數(shù)： 18/19頁
文件大?。?/td> 188K
代理商： 9E4101YFILFT
IDTTM
Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
8
I
2C Table: Watchdog Timer Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
WD4
RW
-
0
Bit 3
WD3
RW
-
0
Bit 2
WD2
RW
-
0
Bit 1
WD1
RW
-
0
Bit 0
WD0
RW
-
0
Pin #
Name
Control Function
Type0
1
PWD
Bit 6
WDEN
Watchdog Enable
R
Disable
Enable
1
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
I
2C Table: VCO Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
N Div8
N Divider Bit 8
RW
-
X
Bit 6
M Div6
RW
-
X
Bit 5
M Div5
RW
-
X
Bit 4
M Div4
RW
-
X
Bit 3
M Div3
RW
-
X
Bit 2
M Div2
RW
-
X
Bit 1
M Div1
RW
-
X
Bit 0
M Div0
RW
-
X
I
2C Table: VCO Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
N Div7
RW
-
X
Bit 6
N Div6
RW
-
X
Bit 5
N Div5
RW
-
X
Bit 4
N Div4
RW
-
X
Bit 3
N Div3
RW
-
X
Bit 2
N Div2
RW
-
X
Bit 1
N Div1
RW
-
X
Bit 0
N Div0
RW
-
X
I
2C Table: Spread Spectrum Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SSP7
RW
-
X
Bit 6
SSP6
RW
-
X
Bit 5
SSP5
RW
-
X
Bit 4
SSP4
RW
-
X
Bit 3
SSP3
RW
-
X
Bit 2
SSP2
RW
-
X
Bit 1
SSP1
RW
-
X
Bit 0
SSP0
RW
-
X
0
M/NEN
M/N Programming
Enable
RW
Disable
-
Enables
prograaming bytes
10-19
Byte 9
-
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Bit 7
The decimal
representation of M
Div (6:0) is equal to
reference divider
value. Default at
power up = latch-in
or Byte 0 Rom
Byte 11
-
The decimal
representation of N
Div (8:0) is equal to
VCO divider value.
Default at power up
= latch-in or Byte 0
Rom table.
Byte 12
-
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to
use ICS Spread %
table for spread
programming.
Byte 13
-
RESERVED
Enable
RESERVED
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