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參數(shù)資料
| 型號(hào)： | 933999360112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 64 X 4 OTHER FIFO, 488 ns, PDIP16 |
| 封裝： | PLASTIC, SOT-38Z, DIP-16 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 125K |
| 代理商： | 933999360112 |
September 1993
16
Philips Semiconductors
Product specication
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
With FIFO empty; SO is held HIGH in anticipation
Notes to Fig.10
1. FIFO is initially empty, SO is held HIGH
2. SI pulse; loads data into FIFO and initiates ripple through process
3. DOR flag signals the arrival of valid data at the output stage
4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the
DOR pulse to the Qn output
5. DOR goes LOW; data shift-out is complete, FIFO is empty again
6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
Fig.10 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation
delay from the DOR pulse to the Qn output.
handbook, full pagewidth
SI INPUT
MGA658
35
Q OUTPUT
n
DOR OUTPUT
VM
(1)
2
ripple through
delay
VM
(1)
6
4
SO INPUT
t PLH
t PHL
VM
(1)
1
t W
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
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| 933999370118 | 64 X 4 OTHER FIFO, 488 ns, PDSO16 |
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| 933999390112 | 64 X 4 OTHER FIFO, 108 ns, PDSO16 |
| 933999380112 | 64 X 4 OTHER FIFO, 108 ns, PDIP16 |
| 0579196702 | 0.5 mm2, BRASS, TIN FINISH, WIRE TERMINAL |
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