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參數(shù)資料
| 型號： | 933999360112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 64 X 4 OTHER FIFO, 488 ns, PDIP16 |
| 封裝： | PLASTIC, SOT-38Z, DIP-16 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 125K |
| 代理商： | 933999360112 |
September 1993
13
Philips Semiconductors
Product specication
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
With FIFO full; SI held HIGH in anticipation of empty location
Notes to Fig.7
1. FIFO is initially full, shift-in is held HIGH
2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
Fig.7 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
handbook, full pagewidth
SI INPUT
MGA660
34
DIR OUTPUT
VM
(1)
2
bubble - up
delay
VM
(1)
5
SO INPUT
t PLH
VM
(1)
1
t W
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
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| 933999370118 | 64 X 4 OTHER FIFO, 488 ns, PDSO16 |
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| 0579196702 | 0.5 mm2, BRASS, TIN FINISH, WIRE TERMINAL |
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