參數(shù)資料
型號: 89HPES8T5AZBBCI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA196
封裝: 15 X 15 MM, 1 MM PITCH, CABGA-196
文件頁數(shù): 4/29頁
文件大?。?/td> 622K
代理商: 89HPES8T5AZBBCI
12 of 29
May 7, 2009
IDT 89HPES8T5A Data Sheet
Figure 5 GPIO AC Timing Waveform
TRX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation
0.3
UI
TRX-IDLE-DET-DIFF-
ENTER TIME
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
TRX-SKEW
Lane to lane input skew
20
ns
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal
Symbol Reference
Edge
Min Max Unit
Timing
Diagram
Reference
GPIO
GPIO[10:0]1
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
Tpw_13b2
2. The values for this symbol were determined by calculation, not by testing.
None
50
ns
Table 11 GPIO AC Timing Characteristics
Parameter
Description
Min1
Typical1
Max1
Units
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
Tdo_13a
Tpw_13b
EXTCLK
GPIO (synchronous output)
GPIO (asynchronous input)
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