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參數(shù)資料
| 型號： | 89HPES8T5AZBBCI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, 1 MM PITCH, CABGA-196 |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 622K |
| 代理商： | 89HPES8T5AZBBCI |
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May 7, 2009
IDT 89HPES8T5A Data Sheet
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
GPIO[8]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[9]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
GPIO[10]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
Signal
Type
Name/Description
APWRDISN
I
Auxiliary Power Disable Input. When this pin is active, it disables the
device from using auxiliary power supply.
CCLKDS
I
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be override by modifying the SCLK bit in the downstream
port’s PCIELSTS register.
CCLKUS
I
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 kHz. This value
may not be overridden.
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside the
PES8T5A and initiates a PCI Express fundamental reset.
Table 5 System Pins (Part 1 of 2)
Signal
Type
Name/Description
Table 4 General Purpose I/O Pins (Part 2 of 2)
相關PDF資料 |
PDF描述 |
|---|---|
| 89HPES8T5AZBBC | PCI BUS CONTROLLER, PBGA196 |
| 89RW30 | SCR |
| 89RW40 | SCR |
| 8AF4NLV | 50 A, 400 V, SILICON, RECTIFIER DIODE |
| 8C443 | PIN/Preamp(Datacom, Telecom) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 89HPES8T5AZBBCI8 | 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 196CABGA - Tape and Reel |
| 89HPES8T5ZBBC | 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays |
| 89HPES8T5ZBBCG | 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays |
| 89HPES8T5ZHBC | 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 324CABGA - Bulk |
| 89HPES8T5ZHBCG | 功能描述:接口-I/O擴展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
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