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參數(shù)資料
| 型號： | 79RC5000 |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 64位微處理器 |
| 英文描述： | MULTI-ISSUE 64-BIT MICROPROCESSOR |
| 中文描述： | 多發(fā)行64位微處理器 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 297K |
| 代理商： | 79RC5000 |
6 of 15
April 10, 2001
79RC5000
!
The RC5000 implements a bus simlar to that of the RC4700. Table 2 lists and describes the RC5000 signals.
System interface
ExtRqst*
Input
External Request.
Signals that the systeminterface needs to submt an external request.
Release*
Output
Release Interface.
Signals that the processor is releasing the systeminterface to slave state
RdRdy*
Input
Read Ready.
Signals that an external agent can now accept a processor read.
WrRdy*
Input
Write Ready.
Signals that an external agent can now accept a processor write request.
ValidIn*
Input
Valid Input.
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the
SysCmd bus.
ValidOut*
Output
Valid Output.
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the
SysCmd bus.
SysAD(63:0)
Input/
Output
System Address/Data bus.
A 64-bit address and data bus for communication between the processor and an external agent.
SysADC(7:0)
Input/
Output
System Address/Data check bus.
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
SysCmd(8:0)
Input/
Output
System Command/data identifier bus.
A 9-bit bus for command and data identifier transmssion between the processor and an external agent.
SysCmdP
Input/
Output
Reserved System Command/data identifier bus parity.
For the RC5000, unused on input and zero on output.
Clock/control interface
SysClock
Input
Master Clock.
Master clock input at the bus frequency. The pipeline clock is derived by multiplying this clock up.
VCCP
Input
Quiet VCC for PLL.
Quiet VCC for the internal phase locked loop.
VSSP
Input
Quiet VSS for PLL.
Quiet VSS for the internal phase locked loop.
Interrupt interface
Int(5:0)*
Input
Interrupt.
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
NMI*
Input
Non-maskable interrupt. Non-maskable interrupt, ORed with bit 6 of the interrupt register.
JTAG interface:
JTDI
Input
JTAG Data In.
Connected directly to JTDO. No JTAG implemented; should be pulled High.
JTCK
Input
JTAG Clock Input.
Unused input; should be pulled High.
Table 3: RC5000 Signal Names and Descriptions (Page 1 of 2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 79RC64574 | Advanced 64-bit Microprocessors Product Family |
| 79RC64575 | Advanced 64-bit Microprocessors Product Family |
| A-1001E | SINGLE DIGIT DISPLAY |
| A-811H | SINGLE DIGIT DISPLAY |
| A-811SR | SINGLE DIGIT DISPLAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 79RC64574 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Advanced 64-bit Microprocessors Product Family |
| 79RC64575 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Advanced 64-bit Microprocessors Product Family |
| 79RC64T574-200DZ | 制造商:Integrated Device Technology Inc 功能描述:MPU RC64574 RISC 64-Bit 200MHz 3.3V 128-Pin PQFP |
| 79RC64T574-250DZ | 制造商:Integrated Device Technology Inc 功能描述:MPU RC64574 RISC 64-Bit 250MHz 3.3V 128-Pin PQFP |
| 79RC64T575-200DP | 制造商:Integrated Device Technology Inc 功能描述:MPU RC64575 RISC 64-Bit 200MHz 3.3V 208-Pin PQFP |
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