參數(shù)資料
型號： 78Q8430-100IGT/F
廠商： Maxim Integrated Products
文件頁數(shù)： 8/88頁
文件大?。?/td> 0K
描述： IC LAN MEDIA ACCESS CTLR 100LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
控制器類型： 以太網(wǎng)控制器，MAC/PHY
電源電壓： 3.3V
電流 - 電源： 230mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
78Q8430 Data Sheet
DS_8430_001
16
Rev. 1.2
3.2.8
Mode Pins
Table 9: Chip Mode Pin Descriptions
Signal
Pin Number
Type
Description
BUSMODE
83
I
BUSMODE, CLKMODE, WAITMODE Configuration
0,0,0 = Sync bus, ext. system clock, memwait act low
0,0,1 = Sync bus, ext. system clock, memwait act high
0,1,0 = Reserved
0,1,1 = Reserved
1,0,0 = Async bus, ext. system clock, memwait act low
1,0,1 = Async bus, ext. system clock, memwait act high
1,1,0 = Async bus, int. system clock, memwait act low
1,1,1 = Async bus, int. system clock, memwait act high
CLKMODE
85
I
WAITMODE
84
I
ENDIAN0
79
I
Data Bus Endian Select
0,0 = Big endian (MSB at high bit positions)
0,1 = Bytes are little endian inside 16-bit words
1,0 = Word endian (MSW at low bit positions)
1,1 = Little endian (MSB at low bit positions)
ENDIAN1
80
I
BOOTSZ1
100
I
GBI Bus Size
BOOTSZ[1:0]: is strapped to indicate the GBI bus size:
00 = Bus is 32 bits wide
01 = Bus is 16 bits wide. Only DATA[15:0] are used.
10 = Bus is 8 bits wide. Only DATA[7:0] are used.
11 = Reserved
BOOTSZ0
1
I
Notes:
1.
The internal PHY should never be powered down when the internal system clock is selected by
the CLKMODE pin (CLKMODE=1)
2.
There is no external visibility for the system clock when the internal clock mode is selected. The
GBI interface must therefore always be used in asynchronous bus mode.
3.2.9
JTAG Pins
Table 10: JTAG Pin Descriptions
Signal
Pin Number
Type
Description
TRST
5
I
Test Reset (active low)
System provided reset for JTAG logic.
TCLK
6
I
Test Clock
System provided clock for JTAG logic.
TMS
3
IU
Test Mode Select
Enables JTAG boundary scan using serial in/serial out ports.
Sampled on rising edge of TCLK.
TDI
4
IU
Test Data In
Serial input port for clocking in test data to be shifted to the
output at the end of the boundary scan chain (TDO).
TDO
81
O
Test Data Out
Serial output port for clocking out test data shifted from the
input at the beginning of the boundary scan chain (TDI).
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