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參數(shù)資料
| 型號(hào)： | 78Q8430-100IGT/F |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 30/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 230mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤(pán) |
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78Q8430 Data Sheet
DS_8430_001
36
Rev. 1.2
STEP 4. Enable the filter. The unicast address filter is enabled by setting the Previous Hit Mask field of
the CAM rule for byte [0] to 0x7F. This step must be done last to prevent an ingressing frame
from matching a partial set of filter rules. All the rules for a filter must be in place before
enabling the filter.
An address filter can be simply activated/deactivated by toggling the value of the Previous Hit Mask field
for the byte [0] CAM rule between 0x7F and 0x00 respectively. The promiscuous mode filter, filter #0,
should not be deactivated in this way.
It is important that STEP 1 deactivates the filter so that no frames are filtered using a partial filter
setting before all relevant rules are written. Step 4 reactivates the filter once the new settings are in
place.
6.7.1.4
Multicast Address Filters
The default CAM rule set supports four multicast address filters. The first, multicast filter #0, serves the same
purpose as the promiscuous mode filter except it applies only to multicast addresses. The last, multicast filter
#3, is the broadcast filter and is reserved for that purpose. The second, multicast filter #1, is the PAUSE filter
and is setup by default to match the PAUSE address. Multicast filter #2 is unused by default and available for
general use. Each filter has two components, the 48-bit address that it matches and a mask that defines
which bits of the address are relevant and which bits are wildcards. Each byte of each address filter has a
CAM rule assigned to it. Table 25 summarizes the association of multicast filter bytes and CAM rules.
Table 25: CAM Rules Associated with Multicast Filter Bytes
Byte [0]
Byte [1]
Byte [2]
Byte [3]
Byte [4]
Byte [5]
M/C Filter #3
0x7F
0x67
0x63
0x4F
0x4B
0x3F
M/C Filter #2
0x7E
0x66
0x62
0x4E
0x4A
0x3E
M/C Filter #1
0x7D
0x65
0x61
0x4D
0x49
0x3D
Note: Bytes are in network transmit order starting with Byte [0].
For an arbitrary multicast filter number N, the following procedure should be used to set the address and
mask values:
STEP 1. Write address and mask byte [0] to CAM rule 0x7C+N as follows.
Reg.
Field
Value to write
CAR
ADDR
0x7C+N
RMR
Data Match
Value of MAC address byte [0]
1
Data Mask
Value of mask byte [0]
1
Previous Hit Match
0x00 to disable the filter
Previous Hit Mask
0x00
RCR
Byte Offset
Retain default: 0x00
Interrupt
Retain default: 0
Control Logic Action
SETMC
Match Control
Retain default: MD
1The LSB of both address byte [0] and mask byte [0] must be set for multicast address filters. If the
LSBs are not set then the address is not multicast and belongs in the unicast filter set.
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| 78Q8430-100IGTR/F | 功能描述:以太網(wǎng) IC 10/100 Ethernet MAC & PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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