2006 Teridian Semiconductor Corporation Rev. 2" />
參數(shù)資料
型號(hào)： 78P2352-IGTR/F
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 7/42頁(yè)
文件大?。?/td> 0K
描述： IC LIU SDH SONET 2CH 128-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 線(xiàn)路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： E4，OC-3，STM1-E
電源電壓： 3.15 V ~ 3.45 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 128-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 128-LQFP-EP（14x14）
包裝： 帶卷 (TR)
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 15 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
REGISTER DESCRIPTION (continued)
ADDRESS N-5: STATUS MONITOR REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7:5
--
R/C
XXX
Reserved.
4
RXLOS
R/C
X
Receive Loss of Signal Indication:
0: Normal operation
1: Loss of signal condition detected
3
RXLOL
R/C
X
Receive Loss of Lock Indication:
This status bit is only defined during a valid input signal at RxP/N or
when RXLOS=0
0: Normal operation
1: Recovered receive clock frequency differs from the reference by
more than +/- 100ppm.
2
--
R/C
X
Unused
1
TXLOL
R/C
X
Transmit Loss of Lock Indication:
This status bit is only defined and valid when using one of the serial
transmit modes utilizing the Tx CDR.
0: Valid transmit input signal detected at SIxDP/N
1: No valid signal detected at SIxDP/N
0
FERR
R/C
X
Transmit FIFO Error Indication:
This bit is set whenever the internal FERR signal is asserted, indicating
that the FIFO is operating at its depth limit. It is reset to 0 when the
FRST pin is asserted.
0: Normal operation
1: Transmit FIFO phase error
ADDRESS N-6, N-7: RESERVED
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7:0
RSVD
R/O
0
Reserved for test.
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