2006 Teridian Semiconductor Corporation Rev." />
參數(shù)資料
型號: 78P2351-IGTR/F
廠商: Maxim Integrated Products
文件頁數(shù): 4/42頁
文件大?。?/td> 0K
描述: LINE INTERFACE UNIT 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E4,OC-3,STM1-E
電源電壓: 3.15 V ~ 3.45 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(16x16)
包裝: 帶卷 (TR)
78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 12 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
REGISTER DESCRIPTION (continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as
required.
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
INPOL
R/W
0
Interrupt Pin Polarity Selection:
0 : Interrupt output is active-low (default)
1 : Interrupt output is active-high
6:2
--
R/W
01000
Reserved for future use
1
MTLOL
R/W
1
TXLOL Error Mask (active low):
Gates the TXLOL register bit to the INTTXB interrupt pin.
0: Mask
1: Pass
0
MFERR
R/W
1
FIERR Error Mask (active low):
Gates the respective FIERR register bit to the INTTXB interrupt pin.
0: Mask
1: Pass
ADDRESS 0-2: I/O CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7:1
--
R/W
XXXXXXX
Unused
0
RCSL
R/W
0
Redundant Channel Enable:
Enables transmit monitor outputs at CMI2P/N pins.
0: Disable
1: Enable
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