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參數(shù)資料
| 型號： | 72V3626L15PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | GREEN, TQFP-128 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 349K |
| 代理商： | 72V3626L15PFG |
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11
IDT72V3626/72V3636/72V3646 CMOS 3.3V Triple Bus SyncFIFOTM
with Bus-Matching 256x36x2, 512x36x2, 1,024x36x2
COMMERCIALTEMPERATURERANGE
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SPM
FS1/
SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
HH
H
↑
X64
X
HH
H
↑↑
64
HH
L
↑
X16
X
HH
L
↑↑
16
HL
H
↑
X8
X
HL
H
↑↑
88
HL
L
↑↑
Parallel programming via Port A
LH
L
↑↑
Serial programming via SD
LH
H
↑↑
Reserved
LL
H
↑↑
Reserved
LL
L
↑↑
Reserved
Following Master Reset, the level applied to the BE/
FWFTinputtochoose
the desired timing mode must remain static throughout FIFO operation. Refer
to Figure 4 (FIFO1 Master Reset) and Figure 5 (FIFO2 Master Reset) for First
Word Fall Through select timing diagrams.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
FourregistersintheseFIFOsareusedtoholdtheoffsetvaluesfortheAlmost-
EmptyandAlmost-Fullflags.ThePortBAlmost-Emptyflag(
AEB)Offsetregister
is labeled X1 and the Port A Almost-Empty flag (
AEA)Offsetregisterislabeled
X2. The Port A Almost-Full flag (
AFA)OffsetregisterislabeledY1andthePort
CAlmost-Fullflag(
AFC)OffsetregisterislabeledY2.Theindexofeachregister
namecorrespondstoitsFIFOnumber.TheOffsetregisterscanbeloadedwith
preset values during the reset of a FIFO, programmed in parallel using the
FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD)
input (see Table 1).
SPM,FS0/SD,andFS1/SENfunctionthesamewayinbothIDTStandard
and FWFT modes.
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
one of the three preset values listed in Table 1, the Serial Program Mode (
SPM)
andatleastoneoftheflagselectinputsmustbeHIGHduringtheLOW-to-HIGH
transition of its Master Reset (
MRS1andMRS2)input.Forexample,toloadthe
presetvalueof64intoX1andY1,
SPM,FS0andFS1mustbeHIGHwhenFlFO1
reset (
MRS1) returns HIGH. Flag Offset registers associated with FIFO2 are
loaded with one of the preset values in the same way with FIFO2 Master Reset
(
MRS2)toggledsimultaneouslywithFIFO1MasterReset(MRS1).Forrelevant
Preset value loading timing diagrams, see Figure 4 and 5.
— PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with
SPMHIGHandFS0andFS1LOW
during the LOW-to-HIGH transition of
MRS1 and MRS2. After this reset is
complete,thefirstfourwritestoFIFO1donotstoredatainRAMbutloadtheOffset
registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the Offset
registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT72V3626, IDT72V3636,
or IDT72V3646, respectively. The highest numbered input is used as the most
significant bit of the binary number in each case. Valid programming values for
the registers range from 1 to 252 for the IDT72V3626; 1 to 508 for the
IDT72V3636; and 1 to 1,020 for the IDT72V3646. After all the Offset registers
are programmed from Port A, the Port C Full/Input Ready flag (
FFC/IRC) is
setHIGH,andbothFIFOsbeginnormaloperation.RefertoFigure8foratiming
diagram illustration for parallel programming of the flag offset values.
— SERIAL LOAD
ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset
with
SPMLOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH
transition of
MRS1andMRS2.Afterthisresetiscomplete,theXandYregister
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/
SEN input is LOW. There are 32-, 36-, or 40-
bitwritesneededtocompletetheprogrammingfortheIDT72V3626,IDT72V3636,
or IDT72V3646, respectively. The four registers are written in the order Y1,
X1, Y2 and finally, X2. The first-bit write stores the most significant bit of the Y1
registerandthelast-bitwritestorestheleastsignificantbitoftheX2register.Each
register value can be programmed from 1 to 252 (IDT72V3626), 1 to 508
(IDT72V3636), or 1 to 1,020 (IDT72V3646).
When the option to program the Offset registers serially is chosen, the Port
AFull/InputReady(
FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (
FFC/
IRC) flag also remains LOW throughout the serial programming process, until
allregisterbitsarewritten.
FFC/IRCissetHIGHbytheLOW-to-HIGHtransition
of CLKC after the last bit is loaded to allow normal FIFO2 operation.
See Figure 9 timing diagram, Serial Programming of the Almost-Full Flag
and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT
Modes).
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) outputs is controlled by Port A Chip
Select (
CSA)andPortAWrite/ReadSelect(W/RA).TheA0-A35outputsare
in the high-impedance state when either
CSA or W/RA is HIGH. The A0-A35
outputs are active when both
CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
NOTES:
1. X1 register holds the offset for
AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for
AEA; Y2 register holds the offset for AFC.
TABLE 1 — FLAG PROGRAMMING
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參數(shù)描述 |
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| 72V3631L15PF | 功能描述:IC SYNCFIFO 512X36 15NS 120-TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標準包裝:45 |
| 72V3631L15PF8 | 功能描述:IC SYNCFIFO 512X36 15NS 120-TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標準包裝:750 |
| 72V3631L15PFG | 功能描述:IC FIFO SYNC 512X36 15NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):有效 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標準包裝:45 |
| 72V3631L15PFG8 | 功能描述:IC FIFO SYNC 512X36 15NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):有效 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標準包裝:750 |
| 72V3631L15PQF | 功能描述:IC SYNCFIFO 512X36 15NS 132QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:132-BQFP 緩沖式 供應(yīng)商器件封裝:132-PQFP（24.13x24.13） 標準包裝:36 |
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