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| 型號： | 72V3626L15PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | GREEN, TQFP-128 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 349K |
| 代理商： | 72V3626L15PFG |
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3
IDT72V3626/72V3636/72V3646 CMOS 3.3V Triple Bus SyncFIFOTM
with Bus-Matching 256x36x2, 512x36x2, 1,024x36x2
COMMERCIALTEMPERATURERANGE
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox
registers. The mailbox registers' width matches the selected bus width of ports
B and C. Each mailbox register has a flag (
MBF1 and MBF2) to signal when
new mail has been stored.
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial
Reset. Master Reset initializes the read and write pointers to the first location
ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram-
ming,or oneofthreepossibledefaultflagoffsetsettings,8,16or64. EachFIFO
has its own, independent Master Reset pin,
MRS1 and MRS2.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
word written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitateaformalreadrequest). ThestateoftheBE/
FWFTpinduringMasterReset
determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC).
The
EFandFFfunctionsareselectedintheIDTStandardmode. EFindicates
whether or not the FIFO memory is empty.
FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEAandAEB)and
aprogrammableAlmost-Fullflag(
AFAandAFC). AEAandAEB indicatewhen
aselectednumberofwordsremainintheFIFOmemory.
AFAandAFCindicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the
Port Clock that writes data into its array.
EFA/ORA,EFB/ORB,AEA,andAEB
are two-stage synchronized to the Port Clock that reads data from its array.
Programmable offsets for
AEA, AEB, AFA, AFC are loaded in parallel using
Port A or in serial via the SD input. The Serial Programming Mode pin (
SPM)
makes this selection. Three default offset settings are also provided. The
AEA
and
AEBthresholdcanbesetat8,16or64locationsfromtheemptyboundary
and the
AFAandAFCthresholdcanbesetat8,16or64locationsfromthefull
boundary. All these choices are made using the FS0 and FS1 inputs during
Master Reset.
Two or more FIFOs may be used in parallel to create wider data paths.
Suchawidthexpansionrequiresnoadditional,externalcomponents. Further-
more, two IDT72V3626/72V3636/72V3646 FIFOs can be combined with
unidirectional FIFOs capable of First Word Fall Through timing (i.e. the
SuperSync FIFO family) to form a depth expansion.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72V3626/72V3636/72V3646 are characterized for operation from
0
°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
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| 7305-0-15-15-47-14-04-0 | BRASS, GOLD FINISH, PCB TERMINAL |
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參數(shù)描述 |
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| 72V3631L15PF | 功能描述:IC SYNCFIFO 512X36 15NS 120-TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應商器件封裝:120-TQFP（14x14） 標準包裝:45 |
| 72V3631L15PF8 | 功能描述:IC SYNCFIFO 512X36 15NS 120-TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應商器件封裝:120-TQFP（14x14） 標準包裝:750 |
| 72V3631L15PFG | 功能描述:IC FIFO SYNC 512X36 15NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):有效 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應商器件封裝:120-TQFP（14x14） 標準包裝:45 |
| 72V3631L15PFG8 | 功能描述:IC FIFO SYNC 512X36 15NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):有效 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應商器件封裝:120-TQFP（14x14） 標準包裝:750 |
| 72V3631L15PQF | 功能描述:IC SYNCFIFO 512X36 15NS 132QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:132-BQFP 緩沖式 供應商器件封裝:132-PQFP（24.13x24.13） 標準包裝:36 |
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