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參數(shù)資料
| 型號： | 72235LB25JGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 2K X 18 OTHER FIFO, 15 ns, PQCC68 |
| 封裝： | GREEN, PLASTIC, LCC-68 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 178K |
| 代理商： | 72235LB25JGI |
7
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 22, 2008
When the
LD pin is LOW and WEN is HIGH, the WCLK input is disabled;
then a signal at this input can neither increment the write offset register pointer,
nor execute a write.
Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe
LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-
to-HIGH transition of the read clock (RCLK). The act of reading the control
registers employs a dedicated read offset register pointer. (The read and write
pointers operate independently).
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (
FL)
FLisgroundedtoindicateoperationintheSingleDeviceorWidthExpansion
mode. In the Depth Expansion configuration,
FLisgroundedtoindicateitisthe
first device loaded and is set to HIGH for all other devices in the Daisy Chain.
(See Operating Configurations for further details.)
WRITE EXPANSION INPUT (
WXI)
Thisisadualpurposepin.
WXIisgroundedtoindicateoperationintheSingle
Device or Width Expansion mode.
WXI is connected to Write Expansion Out
(
WXO) of the previous device in the Daisy Chain Depth Expansion mode.
READ EXPANSION INPUT (
RXI)
Thisisadualpurposepin.
RXIisgroundedtoindicateoperationintheSingle
Device or Width Expansion mode.
RXI is connected to Read Expansion Out
(
RXO) of the previous device in the Daisy Chain Depth Expansion mode.
OUTPUTS:
FULL FLAG(
FF)
When the FIFO is full,
FF will go LOW, inhibiting further write operations.
When
FF is HIGH, the FIFO is not full. If no reads are performed after a reset,
FFwillgoLOWafterDwritestotheFIFO. D=256writesfortheIDT72205LB,
512fortheIDT72215LB,1,024fortheIDT72225LB,2,048fortheIDT72235LB
and 4,096 for the IDT72245LB.
The
FFisupdatedontheLOW-to-HIGHtransitionofthewriteclock(WCLK).
EMPTY FLAG/ (
EF)
WhentheFIFOisempty,
EFwillgoLOW,inhibitingfurtherreadoperations.
When
EF is HIGH, the FIFO is not empty.
The
EFisupdatedontheLOW-to-HIGHtransitionofthereadclock(RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full Flag (
PAF) will go LOW when FIFO
reaches the Almost-Full condition. If no reads are performed after Reset (
RS),
the
PAFwillgoLOWafter(256-m)writesfortheIDT72205LB,(512-m)writes
for the IDT72215LB, (1,024-m) writes for the IDT72225LB, (2,048–m) writes
for the IDT72235LB and (4,096–m) writes for the IDT72245LB. The offset “m”
is defined in the FULL offset register.
If there is no Full offset specified, the
PAF will be LOW when the device is
31 away from completely full for IDT72205LB, 63 away from completely full for
IDT72215LB, and 127 away from completely full for IDT72225LB/72235LB/
72245LB.
The
PAFisassertedLOWontheLOW-to-HIGHtransitionofthewriteclock
(WCLK).
PAFisresettoHIGHontheLOW-to-HIGHtransitionofthereadclock
(RCLK). Thus
PAF is asynchronous.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE)
The ProgrammableAlmost-Empty Flag(
PAE) will go LOW when the read
pointer is "n+1" locations less than the write pointer. The offset "n" is defined in
the EMPTY offset register.
IfthereisnoEmptyoffsetspecified,theProgrammableAlmost-EmptyFlag
(
PAE) will be LOW when the device is 31 away from completely empty for
IDT72205LB, 63 away from completely empty for IDT72215LB, and 127 away
from completely empty for IDT72225LB/72235LB/72245LB.
The
PAEisassertedLOWontheLOW-to-HIGHtransitionofthereadclock
(RCLK).
PAEisresettoHIGHontheLOW-to-HIGHtransitionofthewriteclock
(WCLK). Thus
PAE is asynchronous.
WRITE EXPANSION OUT/HALF-FULL FLAG (
WXO/HF)
This is a dual-purpose output. In the Single Device and Width Expansion
mode, when Write Expansion In (
WXI) and Read Expansion In (RXI) are
grounded, this output acts as an indication of a half-full memory.
Number of Words in FIFO
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
FF PAF
HF PAE EF
00
0
H
L
1 to n(1)
HH
H
L
H
(n + 1) to 128
(n + 1) to 256
(n + 1) to 512
(n + 1) to 1,024
(n + 1) to 2,048
H
129 to (256-(m+1))
257 to (512-(m+1))
513 to (1,024-(m+1))
1,025 to (2,048-(m+1))
2,049 to (4,096-(m+1))
HH
L
H
(256-m)(2) to 255
(512-m)(2)to 511
(1,024-m)(2) to 1,023
(2,048-m)(2) to 2,047
(4,096-m)(2) to 4,095
H
L
H
256
512
1,024
2,048
4,096
L
H
TABLE 1 — STATUS FLAGS
NOTES:
1. n = Empty Offset (Default Values : IDT72205LB n=31, IDT72215LB n = 63, IDT72225LB/72235LB/72245LB n = 127)
2. m = Full Offset (Default Values : IDT72205LB m=31, IDT72215LB m = 63, IDT72225LB/72235LB/72245LB m = 127)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72235LB25JI | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 18 68-Pin PLCC 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 2KX18 68PLCC - Rail/Tube |
| 72235LB25JI8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 18 68-Pin PLCC T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 2KX18 68PLCC - Tape and Reel |
| 72235LB25PF | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72235LB25PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 18 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 2KX18 64TQFP - Tape and Reel |
| 72235LB25PFG | 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 2KX18 64TQFP - Bulk |
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