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| 型號(hào)： | 7026S55J8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 16K X 16 DUAL-PORT SRAM, 55 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | 7026S55J8 |
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6.42
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
15
Functional Description
TheIDT7026providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7026hasanautomaticpowerdownfeaturecontrolled
by CE. The CE controls on-chip power down circuitry that permits the
respectiveporttogointoastandbymodewhennotselected(CE =VIH).
Whenaportisenabled,accesstotheentirememoryarrayispermitted.
Busy Logic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
The BUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
to prevent the write from proceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use any BUSY indication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
TheBUSYoutputsontheIDT7026RAMinmastermode,arepush-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a
master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT7026 are push pull, not open drain outputs. On slaves the BUSYX input
internally inhibits writes.
2. LOW if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. HIGH if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR
= LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level
on the pin.
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupted data in the slave.
Semaphores
The IDT7026 is an extremely fast Dual-Port 16K x 16 CMOS Static
RAMwithanadditional8addresslocationsdedicatedtobinarysemaphore
flags.TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-
PortRAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefined
by the system designer’s software. As an example, the semaphore can
beusedbyoneprocessortoinhibittheotherfromaccessingaportionof
the Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completelyindependentofeachother.Thismeansthattheactivityonthe
left port in no way slows the access time of the right port. Both ports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
Width Expansion with BUSY Logic
Master/Slave Arrays
WhenexpandinganIDT7026RAMarrayinwidthwhileusing BUSY
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slavestobeaddressedinthesameaddressrangeasthemasterusethe
BUSY
signalasawriteinhibitsignal.ThusontheIDT7026RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/Spin=VIH),andtheBUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7026 RAMs.
Truth Table IV —
Address BUSY Arbitration
Inputs
Outputs
Function
CEL
CER
AOL-A13L
AOR-A13R
BUSYL(1)
BUSYR(1)
XX
NO MATCH
H
Normal
H
X
MATCH
H
Normal
X
H
MATCH
H
Normal
L
MATCH
(2)
Write Inhibit(3)
2939 tbl 16
2939 drw 16
MASTER
Dual Port
RAM
BUSYL
BUSYR
CE
MASTER
Dual Port
RAM
BUSYL
BUSYR
CE
SLAVE
Dual Port
RAM
BUSYL
BUSYR
CE
SLAVE
Dual Port
RAM
BUSYL
BUSYR
CE
BUSYL
BUSYR
D
E
C
O
D
E
R
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