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參數(shù)資料
| 型號： | 7026S55J8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 16K X 16 DUAL-PORT SRAM, 55 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 7026S55J8 |
6.42
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
12
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
7026X15
Com'l Only
7026X20
Com'l, Ind
& Military
7026X25
Com'l, Ind
& Military
Unit
Symbol
Parameter
Min.Max.Min.Max.Min.
Max.
BUSY
TIMING (M/S=VIH)
tBAA
BUSY
Access Time from Address Match
____
15
____
20
____
20
ns
tBDA
BUSY
Disable Time from Address Not Matched
____
15
____
20
____
20
ns
tBAC
BUSY
Acce ss Time from Chip Enable Low
____
15
____
20
____
20
ns
tBDC
BUSY
Acce ss Time from Chip Enable High
____
15
____
17
____
17
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
ns
tBDD
BUSY
Disable to Valid Data
____
18
____
30
____
30
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
17
____
ns
BUSY
TIMING (M/S=VIL)
tWB
BUSY
Input to Write(4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
30
____
45
____
50
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
25
____
30
____
35
ns
2939 tbl 14a
7026X35
Com'l, Ind
& Military
7026X55
Com'l, Ind
& Military
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
BUSY
TIMING (M/S=VIH)
tBAA
BUSY
Access Time from Address Match
____
20
____
45
ns
tBDA
BUSY
Disable Time from Address Not Matched
____
20
____
40
ns
tBAC
BUSY
Acce ss Time from Chip Enable Low
____
20
____
40
ns
tBDC
BUSY
Acce ss Time from Chip Enable High
____
20
____
35
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
ns
tBDD
BUSY
Disable to Valid Data(3)
____
35
____
40
ns
tWH
Write Hold After BUSY(5)
25
____
25
____
ns
BUSY
TIMING (M/S=VIL)
tWB
BUSY
Input to Write(4)
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
60
____
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
45
____
65
ns
2939 tbl 14b
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